A 900 mV single-stage class-AB amplifier suitable for the Switched-Opamp technique is presented. To improve the slew-limited characteristics, a Dynamic Current Source (DCS) circuit which boosts the tail currents of the amplifier is proposed. The tail current of the proposed circuit is well defined and independent of technology parameters and supply variations. The tail current of the amplifier is 40 µA with zero differential voltages, while the maximum output current is nearly 900 µA. A single-loop 3rd order Σ-Δ modulator with the proposed amplifier was designed. For a 260 mV 15.625 kHz sinusoidal input signal, the simulated dynamic range of the modulator is 89 dB.

The multilevel dual-channel (MLDC) not-AND (NAND) flash memories cell structures with asymmetrically-doped channel regions between the source and the drain were proposed to enhance read and program verifying speeds. The channel structure of the MLDC flash memories consisted of two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell with asymmetrically-doped channel regions provided the high-speed multilevel reading with a wider current sensing margin and the high-speed program verifying due to the sensing of the discrete current levels. The proposed unique MLDC NAND flash memory device can be used to increase read and program verifying speed.

In this paper, a novel 800 mV beta-multiplier reference current source circuit is presented. In order to cope with the narrow input common-mode range of the Opamp in the reference circuit, the resistive voltage divider was employed. High gain Opamp was designed to compensate for the intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18 µm CMOS process with nominal Vth of 420 mV and -450 mV for n-MOS and p-MOS transistor, respectively. The total power consumption including Opamp is less than 50 µW.

A novel design for temperature-compensated complementary metal-oxide semiconductor (CMOS) voltage reference sources by using the 1st order voltage reference taking into account the electrical property of the conventional current generator was proposed to minimize a temperature coefficient. A temperature coefficient of the proposed voltage reference source was estimated by using the current generator, which operated at smaller or larger temperature in comparison with the optimized operating temperature. The temperature coefficient at temperature range between -40 and 125, obtained from the simulated data by using hynix 0.35 µm CMOS technology, was 3.33 ppm/. The simulated results indicate that the proposed temperature-compensated CMOS voltage reference sources by using the 1st order voltage reference taking into account the electrical properties of the conventional current generator can be used to decrease the temperature coefficient.