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[Author] Kosuke SHIMA(3hit)

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  • Data-Aided SMI Algorithm Using Common Correlation Matrix for Adaptive Array Interference Suppression

    Kosuke SHIMA  Kazuki MARUTA  Chang-Jun AHN  

     
    PAPER-Digital Signal Processing

      Vol:
    E104-A No:2
      Page(s):
    404-411

    This paper proposes a novel weight derivation method to improve adaptive array interference suppression performance based on our previously conceived sample matrix inversion algorithm using common correlation matrix (CCM-SMI), by data-aided approach. In recent broadband wireless communication system such as orthogonal frequency division multiplexing (OFDM) which possesses lots of subcarriers, the computation complexity is serious problem when using SMI algorithm to suppress unknown interference. To resolve this problem, CCM based SMI algorithm was previously proposed. It computes the correlation matrix by the received time domain signals before fast Fourier transform (FFT). However, due to the limited number of pilot symbols, the estimated channel state information (CSI) is often incorrect. It leads limited interference suppression performance. In this paper, we newly employ a data-aided channel state estimation. Decision results of received symbols are obtained by CCM-SMI and then fed-back to the channel estimator. It assists improving CSI estimation accuracy. Computer simulation result reveals that our proposal accomplishes better bit error rate (BER) performance in spite of the minimum pilot symbols with a slight additional computation complexity.

  • Parts Supply Support Method for Leveling Workload in In-Process Logistics

    Noriko YUASA  Masahiro YAMAGUCHI  Kosuke SHIMA  Takanobu OTSUKA  

     
    PAPER

      Pubricized:
    2022/10/20
      Vol:
    E106-D No:4
      Page(s):
    469-476

    At manufacturing sites, mass customization is expanding along with the increasing variety of customer needs. This situation leads to complications in production planning for the factory manager, and production plans are likely to change suddenly at the manufacturing site. Because such sudden fluctuations in production often occur, it is particularly difficult to optimize the parts supply operations in these production processes. As a solution to such problems, Industry 4.0 has expanded to promote the use of digital technologies at manufacturing sites; however, these solutions can be expensive and time-consuming to introduce. Therefore, not all factory managers are favorable toward introducing digital technology. In this study, we propose a method to support parts supply operations that decreases work stagnation and fluctuation without relying on the experience of workers who supply parts in the various production processes. Furthermore, we constructed a system that is inexpensive and easy to introduce using both LPWA and BLE communications. The purpose of the system is to level out work in in-process logistics. In an experiment, the proposed method was introduced to a manufacturing site, and we compared how the workload of the site's workers changed. The experimental results show that the proposed method is effective for workload leveling in parts supply operations.

  • A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing

    Kosuke SHIMAZAKI  Shingo YOSHIZAWA  Yasuyuki HATAKAWA  Tomoko MATSUMOTO  Satoshi KONISHI  Yoshikazu MIYANAGA  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E96-A No:11
      Page(s):
    2114-2119

    This paper presents a VLSI design of a Tomlinson-Harashima (TH) precoder for multi-user MIMO (MU-MIMO) systems. The TH precoder consists of LQ decomposition (LQD), interference cancellation (IC), and weight coefficient multiplication (WCM) units. The LQ decomposition unit is based on an application specific instruction-set processor (ASIP) architecture with floating-point arithmetic for high accuracy operations. In the IC and WCM units with fixed-point arithmetic, the proposed architecture uses an arrayed pipeline structure to shorten a circuit critical path delay. The implementation result shows that the proposed architecture reduces circuit area and power consumption by 11% and 15%, respectively.