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[Author] Kyeong-Yuk MIN(2hit)

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  • A Design of Real-Time JPEG Encoder for 1.4 Mega Pixel CMOS Image Sensor SoC

    Kyeong-Yuk MIN  Jong-Wha CHONG  

     
    PAPER

      Vol:
    E88-A No:6
      Page(s):
    1443-1447

    In this paper, we propose a hardware architecture of real-time JPEG encoder for 1.4 mega pixels CMOS image sensor SoC which can be applied to mobile communication devices. The proposed architecture has an efficient interface scheme with CMOS image sensor and other peripherals for real-time encoding. The JPEG encoder supports the base-line JPEG mode, and processes motion images of which resolution is up to 1280960 (CCIR601 YCrCb 4:2:2,15 fps) by real-time processing. The JPEG encoder supports 8 types of resolution, and can serve the 4 levels of image quality through quantization matrix. The proposed JPEG encoder can transfer encoded motion pictures and raw image data from CMOS image sensor to external device through USB 2.0 and a compressed still image is stored at external pseudo SRAM through SRAM interface. And proposed core can communicate parameters of encoding type with other host by I2C. The proposed architecture was implemented with VHDL and verified for the functions with Synopsys and Modelsim. The encoder proposed in this paper was fabricated in process of 0.18 µ of Hynix semiconductor Inc.

  • A Performance Optimized Architecture of Deblocking Filter in H.264/AVC

    Kyeong-Yuk MIN  Jong-Wha CHONG  

     
    PAPER

      Vol:
    E91-A No:4
      Page(s):
    1038-1043

    In this paper, we propose memory and performance optimized architecture to accelerate the operation speed of adaptive deblocking filter for H.264/JVT/AVC video coding. The proposed deblocking filter executes loading/storing and filtering operations with only 192 cycles for 1 macroblock. Only 244 internal buffers and 3216 internal SRAM are adopted for the buffering operation of deblocking filter with I/O bandwidth of 32 bit. The proposed architecture can process the filtering operation for 1 macroblock with less filtering cycles and lower memory sizes than some conventional approaches of realizing deblocking filter. The efficient hardware architecture is implemented with novel data arrangement, hybrid filter scheduling and minimum number of buffer. The proposed architecture is suitable for low cost and real-time applications, and the real-time decoding with 1080HD (19201088@30 fps) can be easily achieved when working frequency is 70 MHz.