This paper proposes a novel VLSI architecture capable of processing the Lempel-Ziv-based data compression algorithm very fast. The architecture is composed of five main blocks, i.e., a PE-based Match Block, a Consecutive Hit Checker, a Pointer Generator, a Length Generator, and a Code Packer. Flexibility of the PE-based structure makes it possible to adapt to various buffer sizes without any loss of speed or additional control overhead. Since it is designed as a VLSI-oriented architecture, it has simple control logic circuitry. It processes exactly one character per clock cycle and the update of a dictionary buffer is automatically done, therefore it does not require additional accumulated shift operations to prepare for the dictionary buffer. The shift operations have been major problems commonly found in most other architectures. When implemented with the currently available 0.5µm CMOS technology, it is proven by critical path analysis that the architecture can achieve over 100 mega samples (characters) per second with a clock frequency of 100 MHz. This is fast enough for real time data compression for many applications.