In this paper, a robust fractional order memory polynomial pre-distorter with two novel schemes to conduct digital base-band power amplifier pre-distortion is proposed. For the first scheme, fractional order terms are included in the conventional memory polynomial containing the odd and even order polynomial terms, which is called Scheme One. The second scheme, called Scheme Two, simply replaces even order polynomial terms with fractional order polynomial terms to improve the linear performance of power amplifiers. The mathematical expressions for these two schemes are derived. The computer simulations and numerical analysis show that, compared with the conventional pre-distortion methods, 11 dB and 8.5 dB more out-of-band suppression gain can be obtained by Scheme One and Scheme Two, respectively. Corresponding FPGA realization shows that the two schemes are cost-effective in terms of hardware resources.

A novel high-speed and area-efficient Reed-Solomon decoder is proposed, which employs pipelining architecture of minimized modified Euclid (ME) algorithm. The logic synthesis and simulation results of its VLSI implementation show that it not only can operate at a higher clock frequency, but also consumes fewer hardware resources.