This work reports a new technique to suppress the undesirable multiple-triggering effect in the typical diode triggered silicon controlled rectifier (DTSCR), which is frequently used as an ESD protection element in the advanced CMOS technologies. The technique is featured by inserting additional N-Well areas under the N+ region of intrinsic SCR, which helps to improve the substrate resistance. As a consequence, the delay of intrinsic SCR is reduced as the required triggering current is largely decreased and multiple-triggering related higher trigger voltage is removed. The novel DTSCR structures can alter the stacked diodes to achieve the precise trigger voltage to meet different ESD protection requirements. All explored DTSCR structures are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and Very-Fast-Transmission-line-pulsing (VF-TLP) test systems are adopted to confirm the validity of this technique and the test results accord well with our analysis.