In this paper, we present a multiple capture approach to reducing the peak power as well as average power consumption during testing. The basic idea behind is to divide a scan chain into two sub-scan chains, and only one sub-scan chain will be enabled at a time during the scan shift or capture operations. We develop a pattern insertion technique to efficiently deal with the capture violation problem during the capture cycle. In order to alleviate the timing cost due to the insertion of redundant patterns, a scan chain partitioning method incorporated with test pattern reordering is developed to reduce the testing time. Experimental results for large ISCAS'89 benchmark circuits show that the proposed approach can efficiently reduce peak and average power with little timing overhead.