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Yuji SAKAI Kanji OISHI Miki MATSUMOTO Shoji WADA Tadamichi SAKASHITA Masahiro KATAYAMA
As microprocessor units have become faster, DRAMs have also been required to become faster. One of the fast DRAMs is the synchronous DRAM, which transfers data at a high rate. We have developed a 100-MHz Synchronous DRAM using pipeline architecture and new high speed I/O lines method. This paper describes some features of the DRAM and its new pipeline architecture.