Two high-speed sensing techniques suitable for ultrahigh-speed SRAM's are proposed. These techniques can reduce a 64-kb SRAM access time to 71 89% of that of conventional high-speed bipolar SRAM's. The techniques use a small CMOS memory cell instead of the bipolar memory cell that has often been used in conventional bipolar SRAM's for cache and control memories of mainframe computers. Therefore, the memory cell size can also be reduced to 26 43% of conventional cells. A 64-kb SRAM with one of the sensing techniques is fabricated using 0.5-µm BiCMOS technology and achieves a 1.5-ns access time with a 78-µm2 memory cell size. The techniques are especially useful in the development of both ultrahigh-speed and high-density SRAM's, which have been used as cache and control memories of mainframe computers.

A new redundancy technique especially suitable for ultra-high-speed static RAMs (SRAMs) has been developed. This technique is based on a decoding-method that uses two kinds of fuses without introducing any additional delay time. One fuse is initially ON and can be turned OFF afterwards, if necessary, by a cutting process using a focused ion beam (FIB). The other is initially OFF and can be turned ON afterwards by a connecting process using laser chemical vapor deposition (L-CVD). This technique is applied to a 64 kbit SRAM having a 1.5-ns access time. The experimental results obtained through an SRAM chip repaired using this redundancy technique show that this technique does not introduce any increase in the access time and does not reduce the operational margin of the SRAM.

An ECL-CMOS SRAM technology is proposed which features a combination of ECL word drivers, ECL write circuits and low-voltage CMOS cells. This technology assures both ultra-high-speed and high-density. In the ECL-CMOS SRAM,various kinds of noise generated during the write cycle seriously affect the memory performance, because it has much faster access than conventional SRAMs. To overcome this problem, we propose three noise reduction techniques; a noise reduction clamp circuit, an emitter follower with damping capacitor and a twisted bit line structure with "normally on" equalizer. These techniques allow fast accese and cycle times. To evaluate these techniques, a 64-kb SRAM chip was fabricated using 0.5-µm BiCMOS technology. This SRAM has a short cycle time of 2 ns and a very fast access time of 1.5 ns. Evaluation proves the usefulness of these techniques.