Piecewise linear (PWL) circuit modules operating on sigma-delta (ΣΔ) modulated signals and nonlinear signal processors built of these modules are proposed. The proposed module library includes absolute circuits, min/max selectors and negative resistances. Their output signal-to-noise ratio is higher than 50dB when their oversampling ratio is 28. A nonlinear filter and a stochastic resonator are presented as applications of the PWL modules to ΣΔ domain signal processing. The filter is structured with 37% of logic gates consumed by an equivalent filter with a 5-bit parallel signal form.

The arithmetic operations over the finite field GF(pn) has many important applications. There is a need for a fast inverter circuit over the finite field GF(pn), because inversion' is must complicated and lengthy operation. In this paper, we will propose a design method of fast inverter circuit that is based on Euclid's algorithm. The inverter circuit is composed of a number of identical basic circuits. Therefore the designed circuit has a regular and expandable feature and has a modular structure.

This paper presents a novel and successful optimization algorithm for optimizing Multiple-valued Logic (MVL) functions based on Petri net theory. Mathematical properties and Petri net modeling tools to implement MVL systems are introduced. On the basis of these properties and modeling tools, the optimization algorithm can synthesize, analyze and minimize an arbitrary quaternary logic function of n-input variables. The analysis technique of optimization algorithm is a well-established concept from both theories of MVL and Petri nets, and this can be applied to specify and optimize any MVL Petri net system. In this paper, Petri nets of Galois field have been proposed in order to form a complete system, which can be used to realize and construct VLSI circuit of any MVL function. Based on the Petri nets of Galois field and the proposed algorithm, the quaternary minimum and maximum functions have been analyzed, minimized, and designed. These applications have demonstrated the usefulness of optimization algorithm. Based on Petri net theory, the analysis revealed important information about MVL Petri net modeled systems, where this information has been used to evaluate the modeled system and suggest improvements or changes. For evaluation, advantages of the proposed method over a conventional logic minimization method are presented. Also, we have observed that the MVL Petri nets have the following advantages: Designers can exhibit clearly, simply and systematically any complex MVL Petri net nodel, number of concurrent operations is increased, number of places and transitions that are needed to realize a MVL model is very small, and the interconnection problems can be greatly reduced.

A new circuit design of Josephson ternary δ-gate composed of Josephson junction devices is presented. Mathematical theory for synthesizing, analyzing, and realizing any given function in ternary system using Josephson ternary δ-gate is introduced. The Josephson ternary δ-gate is realized using SQUID technique. Circuit simulation results using J-SPICE demonstrated the feasibility and the reliability operations of Josephson ternary δ-gate with very high performances for both speed and power consumption (max. propagation delay time44 ps and max. power consumption2.6µW). The Josephson ternary δ-gate forms a complete set (completeness) with the ternary constants (1, 0, 1). The number of SQUIDs that are needed to perform the operation of δ-gate is 6. Different design with less than 6 SQUIDs is not possible because it can not perform the operation of δ-gate. The advantages of Josephson ternary δ-gate compared with different Josephson logic circuits are as follows: The δ-gate has the property that a simple realization to any given ternary logic function as the building blocks can be achieved. The δ-gate has simple construction with small number of SQUIDs. The δ-gate can realize a large number of ternary functions with small number of input/output pins. The performances of δ-gate is very high, very low power consumption and ultra high speed switching operation.

Novel memory and several logic circuits utilizing the chaotic oscillations produced in SQUIDs are proposed. First, the oscillation modes that can be produced in a SQUID circuit are analyzed. The results of simulation for the SQUID show that there exist four types of oscillations: periodic, subharmonic, chaotic and relaxation oscillations. The bifurcation diagram of oscillation waveforms reveals that the hysteresis phenomena in the relation between the terminal voltage or the current and the external flux appear and that these phenomena can be used for a memory operation. Secondary, novel digital circuits such as memory, Exclusive-OR and full adder circuits are proposed by utilizing the chaotic oscillations. In these digital circuits the chaotic oscillations are made correspond to the logic "1," while the periodic and subharmonic oscillations are made to the logic "0." In order to investigate how these digital circuits perform their functions, computer simulations are made. The simulation results show that the right operations can be achieved.

A digital circuit technique is proposed to process directly bit-stream signals from analog-to-digital converters based on sigma-delta modulation. Newly developed adder and multiplier are fundamental circuit modules for the processing. Using the fundamental modules and up/down counters, other circuit modules such as divider and square root circuits are also realized. The signal processors built of the modules have advantages over multi-bit Nyquist rate processors in circuit scale by the following two distinct features: First, single-bit/multi-bit converters are not needed at the inputs of the processors because the arithmetic modules directly process bit-stream signals. Secondly, the arithmetic modules consist of small number of logic gates. As an application of the technique to digital signal processing for communications, a QPSK demodulator is presented. The demodulator is structured with 40% of logic gates consumed by an equivalent multi-bit demodulator.

In this paper, autonomous 3rd order Josephson junction circuits containing angular variable are analyzed. For the sake of simplicity, easiness and accuracy the piecewise linearizing approximation is emplyed here. Using this method, Poincaré map, bifurcation diagram, attractor dimension and Lyapunov spectrum have been efficiently obtained especially for the chaos in this system. We have also observed the almost one-dimensional feature of the chaos orbit and the fine structure of the chaos oscillation. This chaos has a low attractor dimension nearly equal to that for the quasi-periodic oscillation in non-autonomous 2nd order JJ circuits.

As an application of superconducting devices to electronic engineering, a novel Josephson fuzzy processor is proposed. Since the integrated circuit technologies of superconducting device were successfully developed by using a hard material such as niobium, several kinds of prototype Josephson processor for a general purpose computer have been constructed. Although a Josephson fuzzy processor is a special purpose computer, it is one of the most promising processors suitable for digital application of Josephson elements. The key function of the fuzzy processor is achieved by Mini-Max circuits. In this paper the principle of construction of the Mini-Max circuit using SQUIDs is mainly described in detail and simulation results are illustrated to show how high performance processor can be realized with a reliable operation. Main advantages of the processor are the very simple construction by use of SQUIDs, very high speed operation and ultra low power dissipation.

We propose binary-quantized and spatio-temporally discretized network models of linear diffusion systems and investigate their filtering effect on single-bit sigma-delta (ΣΔ) modulated signals. The network consists of only one kind of elements that add ΣΔ modulated signals and quantize the sum in the form of single-bit signal. A basic one-dimensional network is constructed first. Then, the network is extended into two dimensions. These networks have characteristics equivalent to those of linear diffusion systems in both time and frequency domains. In addition, network noise caused by the quantization in the elements contains low-level low-frequency components and high-level high-frequency components. Therefore, the proposed networks have possibility to be used as signal propagation and diffusion media of ΣΔ domain filters.

Associative memories composed of sparsely interconnected neural networks (SINNs) are suitable for analog hardware implementation. However, the sparsely interconnected structure also gives rise to a decrease in the capability of SINNs for associative memories. Although this problem can be solved by increasing the number of interconnections, the hardware cost goes up rapidly. Therefore, we propose associative memories consisting of multilayer perceptrons (MLPs) with 3-valued weights and SINNs. It is expected that such MLPs can be realized at a lower cost than increasing interconnections in SINNs and can give each neuron in SINNs the global information of an input pattern to improve the storage capacity. Finally, it is confirmed by simulations that our proposed associative memories have good performance.

Estimations on power-delay product as a figure of merit of transferred-electron devices are made for GaAs, InP and Ga0.5In0.5Sb, from a digital device point of view, taking account of the temperature rise. It is shown by comparison of these figures of merit that Ga0.5In0.5Sb is the most promising material for a high speed digital device.

In this paper, oscillation modes produced in a Josephson circuit and its application to digital systems are described. The analysis is performed using an analog simulator to model the Josephson junction, in addition to computer simulation. The experimental results concerning oscillation modes agree well with the simulation results. The main advantage of the mapping for the oscillation modes is that it allows understanding of the relationships among oscillation modes and circuit parameters at first sight. In addition, a novel application of nonlinear oscillation to digital systems is described.

This paper presents a novel and successful logic synthesis method for optimizing ternary logic functions of any given number of input variables. A new optimization algorithm to synthesize and minimize an arbitrary ternary logic function of n-input variables can always lead this function to optimal or very close to optimal solution, where [n (n1)/2]1 searches are necessary to achieve the optimal solution. Therefore, the complexity number of this algorithm has been greatly reduced from O(3n) into O(n2). The advantages of this synthesis and optimization algorithm are: (1) Very easy logic synthesis method. (2) Algorithm complexity is O(n2). (3) Optimal solution can be obtained in very short time. (4) The method can solve the interconnection problems (interconnection delay) of VLSI and ULSI processors, where very fast and parallel operations can be achieved. A transformation method between operational and polynomial domains of ternary logic functions of n-input variables is also discussed. This transformation method is very effective and simple. Design of the circuits of GF(3) operators, addition and multiplication mod-3, have been proposed, where these circuits are composed of Josephson junction devices. The simulation results of these circuits and examples show the following advantages: very good performances, very low power consumption, and ultra high speed switching operation.

Multilayer feedforward neural network (MFNN) trained by the backpropagation (BP) algorithm is one of the most significant models in artificial neural networks. MFNNs have been used in many areas of signal and image processing due to high applicability. Although they have been implemented as analog, mixed analog-digital and fully digital VLSI circuits, it is still difficult to realize their hardware implementation with the BP learning function efficiently. This paper describes a special BP algorithm for the logic oriented neural network (LOGO-NN) which we have proposed as a sort of MFNN with quantized weights and multilevel threshold neurons. Both weights and neuron outputs are quantized to integer values in LOGO-NNs. Furthermore, the proposed BP algorithm can reduce high precise calculations. Therefore, it is expected that LOGO-NNs with BP learning can be more effectively implemented as digital type circuits than the common MFNNs with the classical BP. Finally, it is shown by simulations that the proposed BP algorithm for LOGO-NNs has good performance in terms of the convergence rate, convergence speed and generalization capability.

We consider a network consisting of phase locked loops coupled one another through frequency dividers. When the network structure is rotationally symmetric, spatially periodic simple patterns in terms of the phase of the PLLs are formed. The patterns determine the lock-in frequency of the network. The stability of the pattern is determined by the spatially distributed simple coupling weight patterns. Therefore, a signal with which the network synchronizes is indirectly selected by the weight patterns when several signals are simultaneously applied to the network. The selectivity plays an important role in an intelligent network model.