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[Author] Mitsuyoshi SUZUKI(2hit)

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  • Frequency Re-using Pattern for Forward Link of Orthogonal CDMA Cellular Systems

    Mitsuyoshi SUZUKI  Hideichi SASAOKA  

     
    LETTER-Radio Communication

      Vol:
    E77-B No:6
      Page(s):
    838-842

    This paper studies the effect of frequency re-using patterns on the channel capacity in the forward link of orthogonal code division multiple access (CDMA) cellular systems. The received carrier-to-interference ratio (CIR) determined by computer simulation shows that re-using the same frequency channel on every third sector (3-sector layout) provides superior channel capacity than does every-sector re-use (1-sector layout).

  • A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video

    Shin-ichi URAMOTO  Akihiko TAKABATAKE  Mitsuyoshi SUZUKI  Hiroki SAKURAI  Masahiko YOSHIMOTO  

     
    PAPER-Processors

      Vol:
    E77-C No:12
      Page(s):
    1930-1936

    The hybrid coding with motion compensated prediction and discrete cosine transform (MC+DCT) has been recognized as the standard technique in motion picture coding. In this paper, a motion estimation processor compatible with ITU-T H.261 and MPEG standards is described. A half-pel precision processing unit is introduced with an exhaustive block matching unit for integer-pel precision search. The necessary processing power for the exhaustive block matching is implemented with a 1-dimensional array structure utilizing a sub-sampling technique. In comparison with the conventional 2-dimensional array structure, path of the data transfer is so simple that the low power dissipation characteristic is obtained. The problem of communication bandwidth to the frame memory, which is a bottleneck of half-pel precision motion estimation, is solved by introducing a candidate pixel buffer into the inter-processor data transfer. A static latch circuit with conflict free operation is newly developed for reducing the power consumption. This chip is capable of processing NTSC-resolution video in real-time at the 40 MHz operation. The chip integrates about 540 k transistors in the 121 mm2 die using 0.8 µm double metal CMOS technology.