This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces ED by 45.5% over ep-SFF. The simulations were performed in a 0.1 µm CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency.

In this letter, an improved residual symbol timing offset (STO) estimation scheme is suggested in an orthogonal frequency division multiplexing (OFDM) based digital radio mondiale plus (DRM+) system with cyclic delay diversity (CDD). The robust residual STO estimator is derived by properly selecting the amount of cyclic delay and a pilot pattern in the presence of frequency selectivity. Via computer simulation, it is shown that the proposed STO estimation scheme is robust to the frequency selectivity of the channel, with a performance better than the conventional scheme.