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Naoki HARADA Tamio SAITO Hideyuki OIKAWA Yoji OHASHI Yuji AWANO Masayuki ABE Kohki HIKOSAKA
This paper describes our new technology for creating a highly productive 0. 1 µm gate InGaP/InGaAs HEMT with a GaAs substrate for a millimeter-wave MMIC. We applied a phase-shifting photo lithographic technique and sidewall deposition/etching process to fabricate a 0. 1 µm gate electrode. The fabricated HEMTs showed excellent high-frequency performance; An MSG exceeding 10 dB at 60 GHz. We also fabricated a 60 GHz band, four-stage low-noise amplifier MMIC and demonstrated its superior performance (Gain= 27 dB and NF= 3. 1 dB @61 GHz). These results strongly suggest that our InGaP/InGaAs HEMTs technologies are highly applicable for millimeter-wave applications.
Naoki HARADA Shintaro SATO Naoki YOKOYAMA
The short-channel effect (SCE) in a MOSFET with an atomically thin MoS$_{2}$ channel was studied using a TCAD simulator. We derived the surface potential roll-up, drain-induced barrier lowering (DIBL), threshold voltage, and subthreshold swing (SS) as indexes of the SCE and analyzed their dependency on the channel thickness (number of atomic layers) and channel length. The minimum scalable channel length for a one-atomic-layer-thick MoS$_{2}$ MOSFET was determined from the threshold voltage roll-off to be 7.6,nm. The one-layer-thick device showed a small DIBL of 87,mV/V at a 20 nm gate length. By using high-k gate insulator, an SS lower than 70,mV/dec is achievable in sub-10-nm-scale devices.
Naoki HARADA Shigeru KURODA Kohki HIKOSAKA
A Pt-based gate and photochemical dry etching were developed to fabricate N-InAlAs/InGaAs HEMT ICs. The N-InAlAs/Pt contact showed a Schottky barrier at 0.82 eV, about 0.3 eV larger than ΔEc, and nearly ideal I-V characteristics. Its main disadvantage was the excess penetration of Pt into InAlAs. We proposed a thin-Pt/Ti/Au multilayer gate, more thermally stable than the thick-Pt gate, where Ti layer suppresses the above problem with Pt. The multilayer gate also showed a Schottky barrier (φ) of 0.83 eV and an edeality dactor of 1.1. The high φ value makes it possible to fabricate an E-mode N-InAlAs/InGaAs HEMT. We also developed photochemical selective dry etching using CH3Br gas and a low-pressure mercury lamp. The etching selectivity was 25 at an etch rate of 17 nm/min for InGaAs and 0.7 nm/min for InAlAs. The 1.2-µm-gate E-mode HEMT fabricated using the Pt-based gate and photochemical etching had an excellent peak transconductance of 620 mS/mm with a threshold voltage of +0.03 V. The standard deviation of the threshold voltage of E-mode HEMTs on a 2-inch wafer was 20 mV at an average of +0.088 V. These results indicate the effectiveness of the Pt-based gate and photochemical etching for fabricating N-InAlAs/InGaAs HEMT ICs.