Focusing on gate array and standard cell design LSIs, technology trends in ASIC are discussed. MOS transistors with LDD or modified LDD structures will be effective down to around 0.4 µm. Upon further miniaturization, simple single-drain structure MOS transistors will become prominent. SOI-structure MOS transistors may be even more effective with a smaller short channel effect. The supply voltage should be lowered to 3.3 V for 0.5 µm CMOS LSIs to decrease power dissipation owing to the increase of gate count and operation speed. SOG gate arrays will increase their share of the ASIC market. BiNMOS circuits will be useful under 5 V VDD condition. However, below 3.0 V, CMOS circuits will be preferable. In the near future, tpd of 20-30 ps/gate and 40-50 ps/gate should be attained for GaAs FET and Si-bipolar LSIs, respectively.