This paper discusses an efficient implementation of fault-tolerant digital filters based on the residue number system. In this implementation, a compact residue arithmetic module named the pulse-train residue arithmetic circuit" is effectively employed as the basic module, and an efficient error detection/correction algorithm in which error detections is performed in each basic module and error correction is performed based on the parallelism of residue arithmetic is also employed. Two design methods of fault-tolerant digital filters are newly proposed. In one method the error correcting circuit is imposed in series to the non-redundant system, and in the other the one is imposed in parallel. The prior has an advantage of compact hardware, and the latter has an advantage of high-speed operation. Following the proposed method, a 2nd-order recursive fault-tolerant digital filter with 3 digits is practically implemented, and its fault-tolerant ability is proved by noise injection testing. It is found that the hardware of our digital filter is 70% of the one based on the conventional tripple modular redundancy (TMR), and the mission time improving factor of our digital filter is 150% of the one of the TMR system.

In digital control, it is essential to make the delay time for a large number of multiply-additions small because of sensor feedback. To meet the requirement, an architecture of the reconfigurable parallel processor using field-programmable gate arrays (FPGAs) is proposed. Although the performance is drastically increased in the full custom VLSI implementation, even the reconfigurable parallel processor using FPGAs becomes useful for many practical digital control applications. The performance evaluation shows that the delay time for the resolved acceleration cotrol computation of a twelve-degrees-of-freedom (DOF) redundant manipulator becomes about 70 µs which is about seventeen times faster than that of a parallel processor approach using conventional digital signal processors (DSPs).