Shared multibuffer ATM switches are attractive since they can extend memory bandwidth by the use of multiple independent buffer memories. Although the parallel accessibility allows a considerable improvement in memory bandwidth, a proper assignment of memory addresses to cells is necessary to better utilize the potential bandwidth. In this paper, we present an efficient cell placement strategy for shared multibuffer ATM switches. It is based on a combination of two key concepts, uniform distribution for writes and reference locality for reads. The former is to reduce cell loss ratio due to overflow and write-access conflicts. The latter is to have cells destined for the same output port read from the same buffer memory to minimize read-access conflicts. A single threshold is employed to assign memory locations adaptively depending on the cell distribution among the shared buffer memories. The proposed strategy is shown to outperform the existing ones, in terms of cell loss ratio, cell delay, and throughput. Moreover, the performance gains have been made with a simple control circuit.

Shared buffer ATM switches have been attractive since they can achieve a superior performance in terms of cell loss ratio and throughput with a relatively small buffer size. Shared multi-buffer structures have also been considered by several researchers to enhance the access speed of the cell memory for a large switch. High quality services, however, cannot be provided without reliable operation at each module comprising the ATM switches. In this paper, we present a novel on-line error monitoring technique for shared-buffer ATM switches. The technique detects almost all of the functional errors that could occur in the ATM switches. Moreover, it can detect errors with small hardware overhead and negligible time overhead. An early detection of functional errors in ATM switches could not only reduce the wasted bandwidth due to the transmission of erroneous cells, but greatly enhance the recovery time.