This paper presents the definition and implementation design of a low power data bus encoding scheme dedicated to system on chip video architectures. Trends in CMOS technologies focus the attention on the energy consumption issue related to on-chip global communication; this is especially true for data dominated applications such as video processing. Taking into account scaling effects a novel coupling-aware bus power model is used to investigate the statistical properties of video data collected in the system bus of a reference hardware/software H.263/MPEG-4 video coder architecture. The results of this analysis and the low complexity requirements drive the definition of a bus encoding scheme called CDSPBI (Coupling Driven Separated Partial Bus Invert), optimized ad-hoc for video data. A VLSI implementation of the coding circuits completes the work with an area/delay/power characterization that shows the effectiveness of the proposed scheme in terms of global power saving for a small circuit area overhead.

In this paper a digital frequency domain RFI (Radio Frequency Interference) cancellation scheme for DMT (Discrete Multitone) based VDSL (Very high speed Digital Subscriber Line) systems is presented. The proposed algorithm has been optimized and characterized in terms of complexity and performance. Optimizations were also performed from an implementation point of view by deducing key dependencies among our RFI model coefficients that let us drastically reduce the size of the memories involved. System simulations showed the effectiveness of the canceller: in terms of VDSL performance parameters such as bit rate, the optimized cancellation scheme recovers almost totally the performance degradation due to RFI.