A reliable antifuse scheme has been very hard to build, which has precluded its implementation in DRAM products. We devised a very reliable multi-cell structure to cope with the large process variation in the DRAM-cell-capacitor type antifuse system. The programming current did not rise above 564 µA even in the nine-cell case. The cumulative distribution of the successful rupture in the multi-cell structure could be curtailed dramatically to less than 15% of the single-cell's case and the recovery problem of programmed cells after the thermal stress (300) had disappeared. In addition, we also presented a Post-Package Repair (PPR) scheme that could be directly coupled to the external high-voltage power rail via an additional pin with small protection circuits, saving the chip area otherwise consumed by the internal pump circuitry. A 1 Gbit DDR SDRAM was fabricated using Samsung's advanced 50 nm DRAM technology, successfully proving the feasibility of the proposed antifuse system implemented in it.

We developed a method for analysis of boron penetration and gate depletion using N+ and P+ dual-gate PMOSFETs. An N+ gate PMOSFETs, which is immune to boron penetration and gate depletion, exhibited the threshold voltage shifts and fluctuation in P+ gate PMOSFETs fabricated using identical N- substrates. We showed the importance of Vth fluctuation analysis and found that the Vth fluctuation in N+ gate PMOSFETs was negligible, but, the Vth fluctuation in P+ gate PMOSFETs was significant, indicating that the Vth fluctuation in P+ gate PMOSFETs was dominated by boron penetration. It was also shown, for the first time, that boron penetration occurred with gate depletion, and gate depletion must be very strong to suppress boron penetration. The dual-gate PMOSFET method makes it possible to select high-performance G-bit DRAM fabrication processes that are robust against Vth fluctuation.

We studied effects of 50-200-keV electrons on semiconductor devices using BEASTLI (backscattered electron assisting LSI inspection) method. When irradiating semiconduc-tor devices with such high-energy electrons, we have to note two phenomena. The first is surface charging and the second is device damage. In our study of surface charging, we found that a net positive charge was formed on the device surface. The positive surface charges do not cause serious influence for observation so that we can inspect wafers without problems. The positive surface charging may be brought about because most incident electrons penetrate the device layer and reach the conducting substrate of the semiconductor device. For the device damage, we studied MOS devices which were sensitive to electron-beam irradiation. By applying a 400- annealing to electron-beam irradiated MOS devices, we could restore the initial characteris-tics of MOS devices. However, in order to recover hot-carrier degradation due to neutral traps, we had to apply a 900- annealing to the electron-beam irradiated MOS devices. Thus, BEASTLI could be successfully used by providing an apporopri-ate annealing to the electron-beam irradiated MOS devices.

A new electron-beam wafer inspection system has been developed. The system has a resolution of 5 nm or better, and is applicable to quarter-micron devices such as 256 Mbit DRAMs. The most remarkable feature of this system is that a specimen stage is built in the objective lens and allows a working distance (WD) of 0. "WD=0"minimizes the effect of lens aberrations, and maximizes the resolving power. Innovative designs to achieve WD=0 are as follows: (1)A large objective lens of 730-mm width 730-mm depth 620-mm height that serves as a specimen chamber, has been developed. (2)A hollow specimen stage made of non-magnetic materials has been developed.It allows the lower pole piece and magnetic coile of the objective lens inside it. (3)Acoustic motors made of non-magnetic materials are em-ployed for use in vacuum.

Practical linewidth measurement accuracy better than 0.02 µm 3 sigma that meets the production requirement for devices with sub-half micron features, was achieved in a field emission scanning electron-beam metrology system (Hitachi S-7000). In order to establish high accuracy linewidth measurement, it was found in the study that reduction of electron-beam diameter and precise control of operating conditions are significantly effective. For the purpose of reducing electron-beam diameter, a novel electron optical system was adopted to minimize the chromatic aberration which defines electron-beam profile. As a result the electron beam diameter was reduced from 20 nm to 16 nm. In order to reduce measurement uncertainties associated with actual operating conditions, a field emission electron gun geometry and an objective lens current monitor were investigated. Then the measurement uncertainties due to operating conditions was reduced from 0.016 µm to 0.004 µm.