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[Author] Seiichiro ONO(2hit)

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  • Phenomenological Description of Microwave Characteristics of Low-Tc Superconductor by Three-Fluid Model

    Yoshio KOBAYASHI  Hiromichi YOSHIKAWA  Seiichiro ONO  

     
    PAPER

      Vol:
    E80-C No:10
      Page(s):
    1269-1274

    It is shown that a three-fluid model, which was successfully introduced to explain microwave characteristics of high-Tc superconductors phenomenologically, is suit also to explain those of low-Tc superconductors. In this model, the two contributions of a residual normal electron, in addition to a super and a normal electron in the two-fluid model, and of the temperature (T) dependence of momentum relaxation time τ for the two normal electrons are taken into account. Measured results of the T dependence of surface resistance Rs for a Nb film with critical temperature Tc9.2K agree very well with an Rs curve calculated using the present model, where a residual surface resistance at T0K, Rso, and the T dependence of τ were determined using the surface reactance at 0K Xso37.6mΩ calculated using the BCS theory to fit a calculated Rs curve with the measured values as a function of T. Furthermore, microwave characteristics predicted from the BCS theory cannot be explained phenomenologically using the conventional two-fluid model. This difficulty can be solved by using an improved two-fluid model, called the two-fluid (τ) model, where the T dependence of τ is taken into account. Finally the frequency dependence of Rs calculated for the Nb film is f1.9 for the BCS theory and f2.0 for the three-fluid (τ) model on the assumption of the frequency independence of τ.

  • NAND Gate for SFQ Logic Circuits

    Hiroaki MYOREN  Seiichiro ONO  Susumu TAKADA  

     
    PAPER-Digital Applications

      Vol:
    E83-C No:1
      Page(s):
    81-84

    We propose a universal NAND logic gate based on single flux quantum (SFQ) logic. The NAND gate enables the construction of any logic circuits. In the proposed gate, three superconducting loops share two Josephson junctions (JJs). The critical currents of the JJs were designed to allow each of any two loops to trap an SFQ at the same time. We simulated dynamic operation of this NAND gate. The results show that the NAND gate can operate with a delay time of 45 ps, and the power consumption of this circuit is close to 0.06 µW/gate.