Among the broadband wireless communication standards utilized to satisfy the demand for multimedia services, time division duplexing (TDD) is satisfactory for the asymmetric data transmission emphasized in Internet services. In this system, the transition between receiving a frame and transmitting a response must be bounded for an effective use of radio resources. However, the minimized inter-frame space-time requires high processing power. The aim of the present paper is to gain insight into the time latency at the turn-around time of a TDD operation. We also propose a simplified new processor, which is a terminal device-friendly architecture that includes prediction and preparation to support processing of burst-type traffic.