In wireless communications, a smart antenna system utilizes an antenna array to acquire the spatial signatures of transmitted signals. This system uses the difference in the spatial signatures or the direction of arrival (DOA) of signals to correctly obtain the desired signal. This can reduce co-channel interference, mitigate the fading phenomenon caused by multipath transmissions, improve the communication quality and increase the system capacity. The purpose of this paper is to evaluate the performance of smart antennas using four beamforming algorithms applied to a wideband code division multiple access (W-CDMA) system. The simulation results show that, based on the same power consumption at the transceiver and using a Rake receiver, a W-CDMA system with a smart antenna can operate at a lower bit error rate at the specific signal to noise ratio (SNR). Moreover, the smart antenna system accommodates more users at the specific signal to interference ratio (SIR), even though a certain angle difference exists between the actual DOAs and the estimated DOAs.

An efficient architecture for a FPGA symmetry FIR filter is proposed that employs 2-bit parallel-distributed arithmetic (2-bit PDA). The partial product is pre-calculated and saved into the distributed ROM. This eliminates the large amount of logic needed to compute multiplication results. The proposed architecture consumes less area and offers higher speed operation because the multiplier is omitted.

The software-defined radio technique translates the traditional hardware radio platform to a flexible software radio platform that can support multiple air interface standards. This work proposes an efficient IF processing architecture based on software-defined radio for 2G GSM/IS-95 and 3G W-CDMA systems. Hardware complexity is estimated by fixed-point simulation. IF processing architecture should be highly flexible and minimally complex. Firstly, a carrier channel is selected from a wide frequency band using a high-resolution numerically controlled oscillator (NCO). Wide-range interpolation/decimation is performed by the cascaded integrator comb (CIC) filter that involves no multiplier nor stores filter coefficients. Both the desired narrowband and the desired wideband signals can be extracted. The look-up table (LUT), based on the distributed arithmetic (DA) algorithm is used to implement the finite impulse response (FIR) filter. Therefore, a small area and high speed can be achieved. The errors caused by truncation, quantization, rounding-off and overflow are predicted using a fixed-point simulation. These predictions will help to evaluate the word-length for VLSI implementation. Finally, ALTERA APEX20KE is used as a target device. One hundred thousand gates are used for the implementation. Thus, the proposed architecture has high processing flexibility and small area.