This paper considers a more generalized capacitor that can decrease its width using its own electrical force. We consider a model in which the capacitor with plate distance d is coupled with repulsive mechatronical potential energy, which is proportional to 1/dn. In the conventional case, n is considered to be approximately very large. In our capacitor model, there is a stable point between attractive electrical force and repulsive mechatronical force. In this system, electrostatic energy is equal to the sum of mechatronical potential energy and energy dissipation. Moreover, the mechatronical potential energy is 1/n times smaller than the electrostatic energy. All energies, including the electrostatic energy, potential energy, and energy dissipation, are proportional not to ordinary value V2, but to V2/(n-1)+2, where V is the power supply voltage. This means the voltage dependence of energy is unusual. It is strongly dependent on the capacitor matter, i.e., on the characteristics of the mechatronical system. In addition, the energy dissipation of the system can be reduced to zero using the adiabatic charging process.

This report describes a concrete method for realizing adiabatic charging reversible logic. First, we investigate the stabilization properties of a charge recycle regenerator using a switched capacitor circuit by SPICE simulation and an analytical method. In the N-step case, we proved that a step waveform is spontaneously generated. Next, for combinational logic, we propose an adiabatic charging binary decision diagram logic gate (AC-BDD) that uses this regenerator. The AC-BDD uses pass transistor logic based on a BDD, which is suitable for adiabatic logic. 8-bit AC-BDD multipliers were fabricated, and it is clarified that power consumption is reduced to 15% that of the same-rule-designed CMOS at 1 V and 1 MHz. Finally, we propose clocked energy reversible logic (CERL) that maintains the CMOS architecture for CMOS compatibility. CERL can reduce the clocked energy, which is used for charging the clock load capacitance, to 10% that of CMOS by using a power clock from the charge recycle regenerator.