OPKFDDs (Ordered Pseudo-Kronecker Functional Decision Diagrams) are a data structure that provides compact representation of Boolean functions. The size of OPKFDDs depends on a variable ordering and on decomposition type choices. Finding an optimal representation is very hard and the size of the search space is n! 32n-1, where n is the number of input variables. To overcome the huge search space of the problem, a genetic algorithm is proposed for the generation of OPKFDDs with minimal number of nodes.

In this paper, an efficient approach to the synthesis of CA (Cellular Architecture) -type FPGAs is presented. To exploit the array structure of cells in CA-type FPGAs, logic expressions called Maitra terms which can be mapped directly to the cell arrays are generated by using ETDDs (EXOR Ternary Decision Diagrams). Since a traversal of the ETDD is sufficient to generate a Maitra term which takes O (n) steps where n is the number of nodes in the ETDD, Maitra terms are generated very efficiently. The experiments show that the proposed method generates better results than existing methods.

It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of multiple interconnect faults.