Three primary wiring capacitance components for multi-layer interconnect structure in sub-micron LSI were analyzed by using 2D/3D simulators, and an influence of neighboring wiring was investigated as a three-body problem. The investigated neighboring wiring are three kinds, and they are same-layer, upper-layer and under-layer wiring. An analytical model of each capacitance component was proposed for LPE (Layout Parameter Extraction) system, and its accuracy and application limit were discussed. This new model can estimate each capacitance component of complicated interconnect structure within 20% error.