The Phase Locked Loop (PLL) for clock recovery used in a single chip 155. 52 Mb/s4-Ch CMOS LSI (QPLC) for SONET/SDH termination is described in this letter. This LSI is the first quad-channel ATM physical layer controller chip in which each channel has a clock recovery PLL achieving 55ps rms jitter, using current regulated constant amplitude differential VCO and the triple well structure.

With the spread of broadband and wireless Internet access, there is a growing need for a nomadic network environment that enables the use of network services anywhere, via various access media. In a nomadic network environment, however, the connectivity is decreased because users move among different access networks, and the bandwidth is narrow and fluctuating, especially for radio propagation in wireless networks. To solve these problems, we propose a multilink system with three key functions: IPinIP tunneling, dynamic distribution of packets, and reordering of distributed packets. In particular, our distribution function includes a novel algorithm based on available bandwidth estimation. A prototype of our system was evaluated through experiments using real wireless environments and its efficiency is discussed.