A current folded mixer achieving low 1/f noise for low power direct conversion receivers is proposed. The proposed mixer topology decouples the design tradeoffs between noise figure, conversion gain and third order intermodulation distortion. Comparisons with the conventional current-reuse injection topology, the current folded mixer with 1/f noise minimized shows significant improvements. Experimental design on 2.4-GHz band and with 0.18-µm CMOS technology has revealed the advantages of the newly proposed topology.

The paper presents a dual-band switchable low noise amplifier implemented in 0.25-µm CMOS technology for 5-GHz wireless multimedia applications. The high-speed wireless multimedia applications call for broadband design techniques for RF circuits. Instead of using conventional broadband techniques not well suitable for CMOS implementation, a dual-band switchable load is proposed for broadband LNA design. The dual-band switchable load enables the LNA operate at the lower or the upper band at 5-GHz band by a 1-bit control signal. The LNA exhibits over 17 dB power gain, 3.5 dB noise figure and input 1-dB compression point -23 dBm in both frequency bands. It draws 9.5 mA from 2.5 V supply. The power gain remains larger than 16 dB as temperature varies from -5 to 65.

A circuit technique to correct Vdd/PM distortion and improve efficiency as supply modulation of cascode class-E PAs has been proposed. The experimental result shows that the phase distortion can be improved from 20 degrees to 5 degrees. Moreover, a system co-simulation result demonstrated that the EVM can be improved from -17 dB to -19 dB.

A CMOS low noise amplifier (LNA) for low-power ultra-wideband (UWB) wireless applications is presented. To achieve low power consumption and wide operating bandwidth, the proposed LNA employing stagger tuning technique consists of two stacked common-source stages with different resonant frequencies. This work is implemented in 0.18-µm CMOS process and shows a 2.4-9.4-GHz bandwidth. The amplifier provides a maximum forward gain (S21) of 10.9 dB while drawing 7.1 mW from a 1.8-V supply. A noise figure as low as 4.1 dB and an IIP3 of -3.5 dBm have been demonstrated.

There is increasing interest using CMOS circuits for highly integrated high frequency wireless telecommunications systems. This paper reviews recent works in transceiver architectures, circuits and devices technology for CMOS RFIC application. A number of practical problems those must be resolved in CMOS RFIC design are also discussed.