Due to the structure complexity, it is difficult to display structure of large-scale network fully. To solve the problem, this paper research on network simplification and accelerating drawing. Specific research content includes accelerated network layout based on quadtree and community geometric constrain, aiming to provide overall situation perception of network topology. Experiment results show that this method can quickly visualize complex structure of large-scale network, and present overall situation and structural characteristics of the network by clear and understandable visual expression, and contribute to mining and awareness of network connection mode and structural characteristics.

The proliferation of many-core architectures has led to the explosive development of parallel applications using programming models, such as OpenMP, TBB, and Cilk/Cilk++. With increasing number of cores, however, it becomes even harder to efficiently schedule parallel applications on these resources since current many-core runtime systems still lack effective mechanisms to support collaborative scheduling of these applications. In this paper, we study feedback-driven adaptive scheduling based on work stealing, which provides an efficient solution for concurrently executing a set of applications on many-core systems. To dynamically estimate the number of cores desired by each application, a stable feedback-driven adaptive algorithm, called SAWS, is proposed using active workers and the length of active deques, which well captures the runtime characteristics of the applications. Furthermore, a prototype system is built by extending the Cilk runtime system, and the experimental results, which are obtained on a Sun Fire server, show that SAWS has more advantages for scheduling concurrent parallel applications. Specifically, compared with existing algorithms A-Steal and WS-EQUI, SAWS improves the performances by up to 12.43% and 21.32% with respect to mean response time respectively, and 25.78% and 46.98% with respect to processor utilization, respectively.

In this paper, a highly linear and low noise CMOS active RF tracking filter for a digital TV tuner is presented. The Gm cell of the Gm-C filter is based on a dynamic source degenerated differential pair with an optimized transistor size ratio, thereby providing good linearity and high-frequency operation. The proposed RF tracking filter architecture includes two complementary parallel paths, which provide harmonic rejection in the low band and unwanted signal rejection in the high band. The fabricated tracking filter based on a 0.13 µm CMOS process shows a 48860 MHz tracking range with 30–32 dB 3rd order harmonic rejection, a minimum input referred noise density of 2.4 nV/, and a maximum IIP3 of 0 dBm at 3 dB gain while drawing 39 mA from a 1.2-V supply. The total chip area is 1 mm0.9 mm.