VLSI implementation of the network for a highly parallel computer system by three ASIC chip-set and some related results are described. The chip-set consists of two network-component chips, BMU and SRC, with which the crossbar-like network of arbitrary size can be realized, and a versatile network controller, TCU. New FIFO circuit, inter-chip pipelined data transmission scheme and novel cooperation method between computation and communication called 'FIFO emulation' were introduced in conjunction with communication overheads in parallel processing to enhance effective computing performance and actual transfer rate. The chip set employs synchronous 9 bit bus with peak date transmission rate of 20 MB/sec/channel. All chips are fabricated in 1.2 µm two layer AL N-well CMOS technology, containing 350 k, 25 k and 165 k transistors, respectively. Experiments shows that measured communication overhead is less than 30% where the ratio of computing in MFLOPS and communication in Mword/sec was 1, and 'FIFO emulation' scheme reduces communication time by 21% in the same case.