This work deals with thermal-noise modeling for silicon vertical bipolar junction transistors (BJTs) and relevant integrated circuits (ICs) operating at low currents. The two-junction BJT compact model is consistently derived from the thermal-noise generalization of the Shockley semiconductor equations developed in work which treats thermal noise as the noise associated with carrier velocity fluctuations. This model describes BJT with the Itô non-linear stochastic-differential-equation (SDE) system and is suitable for large-signal large-fluctuation analysis. It is shown that thermal noise in silicon p-n-junction diode contributes to "microplasma" noise. The above model opens way for a consistent-modeling-based design/optimization of bipolar device noise performance with the help of theory of Itô's SDEs.

The theoretical modelling bandgap narrowing and percentage of ionized impurity atoms for uncompensated uniformly doped silicon containing conventional impurities (B, P, As, Sb) under thermodynamic-equilibrium conditions is presented. As distinct from existing approaches, this modelling is valid for impurity concentrations up to electrically-active-impurity-concentration limits and for the temperature range from 40 K up to 400 K. A relevant and efficient calculation software is proposed. The results of the calculations are compared with the results extracted by many authors from measurement data. A good agreement between these results is noted and possible reasons of some discrepancies are pointed out. The present modelling and software can be used for investigation of BJT charge-neutral regions as well as diffused or implanted resistors.