Motion blur in TFT-LCD is caused by sample and hold characteristic, slow response time of liquid crystal, and the inconsistency between object tracking of the human eye and the actual object location. In order to solve this problem, a high frame rate driving method based on motion estimation and motion compensation has been applied to LCD products. However, as the required processing time of motion estimation increases in LCD TV and monitor systems, real-time video image processing becomes more difficult. Frame interpolation through the large macro block (MB) size has limitations to detect small objects. So, this paper proposes the efficient motion estimator architecture which uses seven kinds of macro blocks to enhance the accuracy of motion estimation and combines the parallel processing with pre-computation technology and hardware optimization for high-speed processing. Also, for increased efficiency in the hardware architecture, we employed an I2C (Inter Integrated Circuit) communication unit to control the key parameters easily through the personnel computer. Simulation results show that the critical path at the motion estimator is reduced by about 27.47% compared to the conventional structure. As a result, the proposed motion estimator will be applicable for the high-speed frame interpolation of variable video.

This paper proposes Burst Error Resilient coding (BRC) technology in mobile broadcasting network. The proposed method utilizes Scalable Video Coding (SVC) and Forward Error Correction (FEC) to overcome service outage due to burst loss in mobile network. The performance evaluation is performed by comparing PSNR of SVC and the proposed method under MBSFN simulation channel. The simulation result shows PSNR of SVC equal error protection (EEP), unequal error protection (UEP) and proposed BRC using Raptor FEC code.

Applying Distributed Video Coding (DVC) to mobile devices that have limited computation and power resources can be a very challenging problem due to its high-complexity decoding. To address this, this paper proposes a DVC bitstream organizer. The proposed DVC bitstream organizer reduces the complexity associated with repetitive channel decoding and SI generation in a flexible manner. It allows users to choose a means of minimizing the computational complexity of the DVC decoder according to their preferences and the device's resource limitations. An experiment shows that the proposed method increases decoding speeds by up to 25 times.