This paper presents an 8-bit 200M-sample/s (Ms/s) analog-to-digital converter (ADC) applicable to liquid crystal display (LCD) driver systems. The ADC features such circuit techniques as a low-power and high-speed comparator, an open-loop sample-and-hold amplifier with a 3.4-ns acquisition time, a fully differential two step architecture, and a replica circuit. It is fabricated with a 0.8µm BiCMOS process onto an area of only 12mm2 and it dissipates 500mW from a single-5.2V power supply.

This paper presents an enhanced dual-path delta-sigma analog-to-digital converter. Compared with other architectures, the enhanced architecture increases the noise shaping order without any instability problems and displays analog complexity equivalent to the multi-stage noise shaping architecture. Our delta-sigma converter is based on this new architecture. It employs not only doubly-differential structure to reduce common-mode errors in the system-level but also delayed-feed-in structure to mitigate the timing constraint of the feedback signal. Regarding the circuit implementation, the first-order enhancement of the quantization noise shaping is achieved via the use of a switched capacitor circuit technique. The circuit is incorporated into the active adder in a low-distortion structure. The supporting clock generation circuit that provides additional phases of clocks with the enhancement block is also implemented in the CMOS logic gates. A digital dynamic element matching circuit (i.e., segmented data-weighted-average circuit) is designed to reduce mismatch errors caused by the feedback DAC of modulator. A test chip, fabricated in a 0.18-µm CMOS process, provides a signal-to-noise+distortion ratio (SNDR) of 75-dB for a 1.0-MHz signal bandwidth clocked at 40-MHz. The 2nd harmonic is -101 dB and the 3rd harmonic is -94 dB when a -4.5-dB 100-kHz input signal is applied.