In this paper, a new systolic array structure for the extended QR decomposition based recursive least-square (QRD-RLS) equalizer is proposed. The fact that the vectoring and rotation mode coordinate rotation digital computer (CORDIC) processors rotate in the same direction is used to show that the hardware complexity of the systolic array can be reduced. Furthermore, since the vectoring and rotation mode CORDIC processors in the proposed structure rotate simultaneously, operation time is also reduced. The performance of the proposed equalizer is analyzed by observing the flatness obtained by multiplying the frequency responses of the unknown channel with the proposed equalizer. Simulation results through hardware description language (HDL) coding and synthesis show that 23.8% of the chip implementation area can be reduced.

In this paper, a new DA (Distributed Arithmetic) filter implementation technique is presented. Contrary to the conventional DA technique using ROM, the proposed implementation technique avoids the use of ROM since it does not need the combinations of filter coefficients. Furthermore, by using the Radix-16 modified Booth algorithm, implementation complexity of the proposed structure can be reduced. Through the HDL coding and synthesis, it was shown that 41.6% of implementation area can be reduced.