In recent years, heterogeneous devices have been employed frequently in mobile storage systems because a combination of such devices can supply a synergistically useful storage solution by taking advantage of each device. One important design constraint in heterogeneous storage systems is to mitigate I/O performance degradation stemming from the difference between access times of different devices. To this end, there has not been much work to devise proper buffer cache management algorithms. This paper presents a novel buffer cache management algorithm which considers both I/O cost per device and workload patterns in mobile computing systems with a heterogeneous storage pair of a hard disk and a NAND flash memory. In order to minimize the total I/O cost under varying workload patterns, the proposed algorithm employs a dynamic cache partitioning technique over different devices and manages each partition according to request patterns and I/O types along with the temporal locality. Trace-based simulations show that the proposed algorithm reduces the total I/O cost and flash write count significantly over the existing buffer cache algorithms on typical mobile traces.

Since mobile ad-hoc networks have certain constraints, including power shortages, an unstable wireless environment, and node mobility, more power-efficient and reliable routing protocols are needed. Accordingly, this paper propose a new routing protocol, PERRA (Power Efficient Reliable Routing protocol for mobile Ad-hoc networks), that includes the advantages of on-demand protocols, while also providing power- efficient and reliable packet transmission. PERRA uses a new cost function to select the optimum path based on considering the minimum residual energy of the nodes on a path, the total energy consumed by a path to transmit and process a packet, and the path's stability in accordance with the node mobility. As a result, the proposed method increases the power efficiency, decreases the route-reconstructions due to residual power shortages and node mobility, and provides effective route maintenance mechanisms. The performance of PERRA is evaluated by simulations under various conditions.

In this paper, a multi-coded variable spreading gain (MC-VSG) CDMA system employing a binary transmission of MC signals by introducing a level clipper, termed MC-VSG BNet system, is proposed for a possible candidate of wireless personal area network (WPAN) and 3 G cellular applications. With an emphasis on the MC-VSG BNet physical layer and the system performance, we address the concise specification of the MC-VSG BNet system including the spreading code, level clipping, modulation, coding, and frame format. Especially, we focus on the level clipping of multi-level MC signals for both power- and cost-efficient implementation and the VSG code design fir high-rate transmissions. From the receiver performance based on simulation results, in addition to simple receiver structure, an acceptable performance degradation of the MC-VSG BNet system over the existing DS/CDMA system is observed, while guaranteeing an high bit rate transmission.

In disk-based storage systems, non-volatile write caches have been widely used to reduce write latency as well as to ensure data consistency at the level of a storage controller. Write cache policies should basically consider which data is important to cache and evict, and they should also take into account the real I/O features of a non-volatile device. However, existing work has mainly focused on improving basic cache operations, but has not considered the I/O cost of a non-volatile device properly. In this paper, we propose a pattern-aware write cache policy, PAW for a NAND flash memory in disk-based mobile storage systems. PAW is designed to face a mix of a number of sequential accesses and fewer non-sequential ones in mobile storage systems by redirecting the latter to a NAND flash memory and the former to a disk. In addition, PAW employs the synergistic effect of combining a pattern-aware write cache policy and an I/O clustering-based queuing method to strengthen the sequentiality with the aim of reducing the overall system I/O latency. For evaluations, we have built a practical hard disk simulator with a non-volatile cache of a NAND flash memory. Experimental results show that our policy significantly improves the overall I/O performance by reducing the overhead from a non-volatile cache considerably over a traditional one, achieving a high efficiency in energy consumption.

Backlight dimming techniques have been researched much to obtain high power saving on display modules, especially those which are based on LCD. The use of LED as a light source in a backlight module has opened a wider chance to perform local dimming as an improvement of a conservative global dimming approach. However, local dimming techniques are sometimes observed to obtain worse performance than global dimming ones in terms of power saving or image fidelity. We observed that even some of their results show visible artifacts. In this paper, we propose a novel backlight dimming technique called hybrid dimming, which combines local and global dimming approaches effectively. We do local dimming to obtain the initial backlight levels while calculating its SSIM index, which is a human visual system-aware image quality metric. We then make sure that these backlight levels don't exceed the ones obtained from a human visual system-aware global dimming with similar image fidelity. As a result, our proposed method can gain better power saving than a human visual system-aware global dimming and prior local dimming techniques, while making little difference in the image fidelity and suppressing visible block artifacts in the results. Experimental results showed that the proposed technique can achieve up to 14, 2.2, and 2.4 times higher power saving ratio than human visual system-aware global dimming and two well-designed local dimming techniques, respectively.

Modern video compression usually consists of ME/MC (Motion Estimation/Motion Compensation), transform, and quantization of the transform coefficients. Efficient bit allocation technique to distribute available bits to motion parameters and quantized coefficients is an important part of the whole system. A method that is very complex and/or needs buffering of many future frames is not suitable for real time application. We develop an efficient bit allocation technique that utilizes the estimated effect of allocated bits to motion parameter and quantization on the overall quality. We also propose an hierarchical block based ME/MC technique that requires less computations than classical BMA (Block Matching Algorithm) while offering better motion estimation.