The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for cache transistors improves leakage, but impacts cell delay. We show that due to uncorrelated random within-die delay variation, only some (not all) of cells actually violate the cache delay after the above change. We propose to add a spare cache way to replace delay-violating cache-lines separately in each cache-set. By SPICE and gate-level simulations in a commercial 90 nm process, we show that choosing higher Vth, Tox and adding one spare way to a 4-way 16 KB cache reduces leakage power by 42%, which depending on the share of leakage in total cache power, gives up to 22.59% and 41.37% reduction of total energy respectively in L1 instruction- and L2 unified-cache with a negligible delay penalty, but without sacrificing cache capacity or timing-yield.

Recently, we proposed an interference-aware channel segregation based dynamic channel assignment (IACS-DCA). In IACS-DCA, each base station (BS) measures the instantaneous co-channel interference (CCI) power on each available channel, computes the moving average CCI power using past CCI measurement results, and selects the channel having the lowest moving average CCI power. In this way, the CCI-minimized channel reuse pattern can be formed. In this paper, we introduce the autocorrelation function of channel reuse pattern, the fairness of channel reuse, and the minimum co-channel BS distance to quantitatively examine the channel reuse pattern formed by the IACS-DCA. It is shown that the IACS-DCA can form a CCI-minimized channel reuse pattern in a distributed manner and that it improves the signal-to-interference ratio (SIR) compared to the other channel assignment schemes.