This letter proposes a novel modulation classification method for overlapped sources named LRGP involving multinomial logistic regression (MLR) and multi-gene genetic programming (MGGP). MGGP based feature engineering is conducted to transform the cumulants of the received signals into highly discriminative features and a MLR based classifier is trained to identify the combination of the modulation formats of the overlapped sources instead of signal separation. Extensive simulations demonstrate that LRGP yields superior performance compared with existing methods.

The scan segmentation method is an efficient solution to deal with the test power problem; However, the use of multiple capture cycles may cause capture violations, thereby leading to fault coverage loss. This issue is much more severe in at-speed testing. In this paper, two scan partition schemes based on complex networks clustering ara proposed to minimize the capture violations without increasing test-data volume and extra area overhead. In the partition process, we use a more accurate notion, spoiled nodes, instead of violation edges to analyse the dependency of flip-flops (ffs), and we use the shortest-path betweenness (SPB) method and the Laplacian-based graph partition method to find the best combination of these flip-flops. Beyond that, the proposed methods can use any given power-unaware set of patterns to test circuits, reducing both shift and capture power in at-speed testing. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed methods.

Unlimited requirements for system-on-chip (SoC) facilitate three-dimensional (3D) technology as a promising alternative for extending Moore's Law. In spite of many advantages 3D technology provides, 3D technology faces testing issues because of the complexity of 3D design. Therefore, resolving the problem of test optimization and reducing test cost are crucial challenges. In this paper, we propose a novel optimization mechanism of 3D SoCs to minimize test time for mid-bond testing. To make our proposed mechanism more practical, we discuss test cost in mid-bond testing with consideration of manufacturing influence factors. Experimental results on ITC'02 SoC benchmark circuits show that our proposed mechanism reduces mid-bond test time by around 73% on average compared with one baseline solution, furthermore, the mechanism also proves its capacity in test cost reduction.

In this paper, a Boolean algebra approach is proposed to encode various acceptability semantics for abstract argumentation frameworks, where each semantics can be equivalently encoded into several Boolean constraint models based on Boolean matrices and a family of Boolean operations between them. Then, we show that these models can be easily translated into logic programs, and can be solved by a constraint solver over Boolean variables. In addition, we propose some querying strategies to accelerate the calculation of the grounded, stable and complete extensions. Finally, we describe an experimental study on the performance of our encodings according to different semantics and querying strategies.