In industrial control processes, control performance influences the quality of products and utilization efficiency of energy; hence, the controller is necessarily designed according to user-desired control performance. Ideal control performance requires fast response for transient state and maintaining user-specified control performance for steady state. Hence, an algorithm to tune controller parameters to match the requirements for transient state and steady state is proposed. Considering the partial learning ability of the cerebellar model articulation controller (CMAC) neural network, it is utilized as a “tuner” of controller parameters in this study, since then the controller parameters can be tuned in both transient and steady states. Moreover, the fictitious reference iterative tuning (FRIT) algorithm is combined with CMAC in order to avoid problems, which may be caused by system modeling error and by using only a set of closed-loop data, the desired controller can be calculated in an off-line manner. In addition, the controller selected is a proportional-integral-derivative (PID) controller. Finally, the effectiveness of the proposed method is numerically verified by using some simulation and experimental examples.

A novel design of Cerebellar Model Articular Controller (CMAC) is presented in this article. The controller is designed by means of a content addressable memory (CAM) to replace a hash-coding function, which is adopted by generic CMACs to tackle memory space problem how a large space maps into a small one. With a different address mapping method from hash-coding methods, each memory location of the proposed architecture includes two tuples: One is the conceptual address stored in a CAM, and another is the weight associated with the conceptual address stored in a SRAM. The CAM, with capability of fast comparison, is used to determine if any of CAM's content is identical to current conceptual address in parallel. If no match occurs, an associated mask function is triggered to expand searching range, which is centered by current conceptual address with a radius defined by the number of maskable bits. If a location in the CAM carries the similar address, the weight (in SRAM) related to this matching location would be shared and updated by both the current conceptual address and the conceptual address in this location. Therefore, the control noises caused by hash-coding methods can be attenuated significantly in either the training or the recall phases in the proposed architecture. Furthermore, if there is no match in current search, after the mask function is executed, the new conceptual address with an initial weight value would be stored in a CAM cell sequentially indexed by an incremental pointer. Instead of storing the information by scattering it over the memory, the proposed architecture sequentially stores the information by the index of this pointer to increase the memory utilization. Simulation results, (1) one input variable and two input variables cases of function approximations, (2) a truck backer-upper control, demonstrate the plausible performance of the proposed CMAC architecture. The architecture and the design criteria for the proposed controller are also discussed.