In this letter, a simple and robust synchronization algorithm for second generation terrestrial digital video broadcasting (DVB-T2) receivers is proposed. In the proposed detection scheme, the coarse symbol timing is estimated by decimating a correlation output to give a sharper peak timing detection metric. Such a design can improve the timing synchronization accuracy as well as enhance its robustness to frequency selective channels.

The second generation digital terrestrial broadcasting system (DVB-T2) is the first broadcasting system employing MISO (Multiple-Input Single-Output) algorithms. The potential MISO gain of this system has been roughly predicted through simulations and field tests. Of course, the potential MISO SFN gain (MISO-SFNG) differs according to the simulation conditions, test methods, and measurement environments. In this paper, network gains of SISO-SFN and MISO-SFN are theoretically derived. Such network gains are also analyzed with respect to the receive power imbalance and coverage distances of SISO and MISO SFN. From the analysis, it is proven that MISO-SFNG is always larger than SISO SFN gain (SISO-SFNG) in terms of the achievable SNR. Further, both MISO-SFNG and SISO-SFNG depend on the power imbalance, but the network gains are constant regardless of the modulation order. Once the field strength of the complete SFN is obtained by coverage planning tools or field measurements, the SFN service coverage can be precisely calibrated by applying the closed-form SFNG formula.

This paper presents a low-complexity multi-mode fast Fourier transform (FFT) processor for Digital Video Broadcasting-Terrestrial 2 (DVB-T2) systems. DVB-T2 operations need 1K/2K/4K/8K/16K/32K-point multiple mode FFT processors. The proposed architecture employs pipelined shared-memory architecture in which radix-2/22/23/24 FFT algorithms, multi-path delay commutator (MDC), and a novel data scaling approach are exploited. Based on this architecture, a novel low-cost data scaling unit is proposed to increase area efficiency, and an elaborate memory configuration scheme is designed to make single-port SRAM without degrading throughput rate. Also, new scheduling method of twiddle factor is proposed to reduce the area. The SQNR performance of 32K-point FFT mode is about 45.3 dB at 11-bit internal word length for 256QAM modulation. The proposed FFT processor has a lower hardware complexity and memory size compared to conventional FFT processors.