This paper presents a generalized new approach for testing interconnects (for boundary scan architectures) as well as field programmable interconnect chips (FPICs). This approach relies on a structured walking-1 test set in the sense that a structural analysis based on the layout of the interconnect system, is carried out. The proposed structural test method differs from previous approaches as it explicitly avoids aliasing and confounding and is applicable to dense as well as sparse layouts and in the presence of faults in the programmable devices of a FPIC. The proposed method is applicable to both one-step and two-step test generation and diagnosis. Two algorithms with an execution complexity of O(n2), where n is the number of nets in the interconnect, are given. New criteria for test vector compaction are proposed; a greedy condition is exploited to compact test vectors for one-step and two-step diagnosis. For a given interconnect, the two-step diagnosis algorithm requires a number of tests as a function of the number of faults present, while the one-step algorithm requires a fixed number of tests. Simulation results for benchmark and randomly generated layouts show a substantial reduction in the number of tests using the proposed approaches compared with previous approaches. The applicability of the proposed approach to FPICs as manufactured by [1] is discussed and evaluated by simulation.