The search functionality is under construction.
The search functionality is under construction.

Keyword Search Result

[Keyword] SIIT(2hit)

1-2hit
  • Design and Implementation of a Software Tester for Benchmarking Stateless NAT64 Gateways Open Access

    Gábor LENCSE  

     
    POSITION PAPER-Network

      Pubricized:
    2020/08/06
      Vol:
    E104-B No:2
      Page(s):
    128-140

    The Benchmarking Working Group of IETF has defined a benchmarking methodology for IPv6 transition technologies including stateless NAT64 (also called SIIT) in RFC 8219. The aim of our effort is to design and implement a test program for SIIT gateways, which complies with RFC 8219, and thus to create the world's first standard free software SIIT benchmarking tool. In this paper, we overview the requirements for the tester on the basis of RFC 8219, and make scope decisions: throughput, frame loss rate, latency and packet delay variation (PDV) tests are implemented. We fully disclose our design considerations and the most important implementation decisions. Our tester, siitperf, is written in C++ and it uses the Intel Data Plane Development Kit (DPDK). We also document its functional tests and its initial performance estimation. Our tester is distributed as free software under GPLv3 license for the benefit of the research, benchmarking and networking communities.

  • Design and Implementation of the High-Speed IPv6-IPv4 Translator and Analysis of Its Performance

    In-Yeup KONG  Kyong-Yeol LEE  Jung-Tae LEE  

     
    PAPER

      Vol:
    E89-B No:4
      Page(s):
    1136-1143

    In this paper, we propose high performance IPv6-IPv4 translator, which translates all packets between IPv6 networks and IPv4 networks at high speed. In our previous work, we analyzed the performance factors of the existing S/W IPv6-IPv4 translators and proposed the improvement methods of each factor. To realize these methods, we also design and implement the IPv6-IPv4 translator with hardware core for the high-speed translation. To verify functionality of our translator core, the hardware emulation using prototyping as well as simulation is performed. Moreover, we show that our translator core can support high-performance translation.