The address discharge characteristics formed when an address pulse is applied in AC plasma display panels are investigated by changing the ramp-down voltage during the reset period. The address discharge time lag can be reduced when the difference between the ramp-down voltage and the scan-low voltage is set at a high value during the ramp-down period because the loss of the wall charges accumulated between the scan (Y) and address (A) electrodes during the reset period is minimized. In addition, the voltage applied to the X electrode during the ramp-down period can prevent the voltage margin from reduction even though applying high voltage difference on the Y electrodes.