In view of the frequent and complex changes of GNSS visible satellite constellation in attitude determination system, an improved attitude signal simulation algorithm for high dynamic satellite signal simulator is proposed. Based on Software Radio architecture, elevation calculation in the antenna coordinate system and channel state control logic under the condition of carrier attitude changes are introduced into the algorithm to implement synchronous scheduling of visible satellite constellation and attitude signal simulation. This work guarantees the simulator to run constantly and stably for a long time with the advantages of high precision and low complexity. Compared with synchronous positioning results from the receiver, the simulation results show that not only can the output signals of the simulator accurately reflect the carrier's attitude characteristics, but also no step error is generated and the positioning precision is not influenced when visible satellite constellation changes.

This paper describes a BIST circuit for testing SoC integrated multi-channel serializer/deserializer (SerDes) macros. A newly developed packet-based PRBS generator enables the BIST to perform at-speed testing of asynchronous data transfers. In addition, a new technique for chained alignment checks between adjacent channels helps achieve a channel-count-independent architecture for verification of multi-channel alignment between SerDes macros. Fabricated in a 0.13-µm CMOS process and operating at > 500 MHz, the BIST has successfully verified all SerDes functions in at-speed testing of 5-Gbps20-ch SerDes macros.