As many research works are based on some previous results, my paper, namely The Integrated Scheduling and Allocation of High-Level Test Synthesis, makes use of some techniques by T. Kim. However, I did not state explicitly that some parts of my work are based on Kim's approach although I have referred to his paper. I would like to express my deep apology to Kim for not having emphasized Kim's contribution to my work. But my intention was not to steal Kim's ideas. I would like to emphasize the following difference.

I would like to draw the attention of the editorial board of IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences and its readers to a recent paper, Tianruo Yang, "The integrated scheduling and allocation of high-level test synthesis," vol. E82-A, no. 1, January 1999, pp. 145-158. (Here we call this paper the Yang's paper. ) Yang did not give the correct information about the originality of the paper. I will point out that the writings (and the idea accordingly) of section 6 of Yang's paper came from papers [1] and [2].

This paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Data path allocation is achieved by a controllability and observability balance allocation technique which is based on testability analysis at register-transfer level. Scheduling, on other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. Contrary to other works in which the scheduling and allocation tasks are performed independently, our approach integrates scheduling and allocation by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. Additionally, since sequential loops are widely recognized to make a design hard-to-test, a complete (functional and topological) loop analysis is performed at register-transfer level in order to avoid loop creation during the integrated test synthesis process. With a variety of synthesis benchmarks, experimental results show clearly the advantages of the proposed algorithm.