Codes over permutations and multipermutations have received considerable attention since the rank modulation scheme is presented for flash memories. Deletions in multipermutations often occur due to data synchronization errors. Based on the interleaving of several single-deletion-correcting multipermutation codes, we present a construction of multipermutation codes for correcting a burst of at most t deletions with shift magnitude one for t ≥2. The proposed construction is proved with including an efficient decoding method. A calculation example is provided to validate the construction and its decoding method.

In this paper, we propose a group theoretic representation suitable for the rank-modulation (RM) scheme over the multi-cell ranking presented by En Gad et al. By introducing an action of the group of all permutation matrices on the set of all permutations, the scheme is clearly reformulated. Moreover, we introduce the concept of r-dominating sets over the multi-cell ranking, which is a generalization of conventional dominating sets, in the design of rank-modulation rewriting codes. The concept together with the proposed group theoretic representation yields an explicit formula of an upper bound on the size of the set of messages that can be stored in the memory by using RM rewriting codes over multi-cell ranking. This bound enables us to consider the trade-off between the size of the storable message set and the rewriting cost more closely. We also provide a concrete example of RM rewriting code that is not available by conventional approaches and whose size of the storable message set can not be achieved by conventional codes.

In this paper, we propose a construction of non-binary WOM (Write-Once-Memory) codes for WOM storages such as flash memories. The WOM codes discussed in this paper are fixed rate WOM codes where messages in a fixed alphabet of size M can be sequentially written in the WOM storage at least t*-times. In this paper, a WOM storage is modeled by a state transition graph. The proposed construction has the following two features. First, it includes a systematic method to determine the encoding regions in the state transition graph. Second, the proposed construction includes a labeling method for states by using integer programming. Several novel WOM codes for q level flash memories with 2 cells are constructed by the proposed construction. They achieve the worst numbers of writes t* that meet the known upper bound in the range 4≤q≤8, M=8. In addition, we constructed fixed rate non-binary WOM codes with the capability to reduce ICI (inter cell interference) of flash cells. One of the advantages of the proposed construction is its flexibility. It can be applied to various storage devices, to various dimensions (i.e, number of cells), and various kind of additional constraints.

In this letter, three types of constructions for multipermutation codes are investigated by using interleaving technique and single-deletion permutation codes to correct a predetermined number of adjacent deletions. The decoding methods for the proposed codes are provided in proofs and verified with examples. The rates of these multipermutation codes are also compared.

Rapid process scaling and the introduction of the multilevel cell (MLC) concept have lowered costs of NAND Flash memories, but also degraded reliability. For this reason, the memories are depending on strong error correcting codes (ECCs), and this has enabled the memories to be used in wide range of storage applications, including solid-state drives (SSDs). Meanwhile, too strong error correcting capability requires excessive decoding complexity and check bits. In NAND Flash memories, cell errors to neighborhood voltage levels are more probable than those to distant levels. Several ECCs reflecting this characteristics, including limited-magnitude ECCs which correct only errors with a certain limited magnitude and low-density parity check (LDPC) codes, have been proposed. However, as most of these ECCs need the multiple bits in a cell for encoding, they cannot be used with multipage programing, a high speed programming method currently employed in the memories. Also, binary ECCs with Gray codes are no longer optimal when multilevel voltage shifts (MVSs) occur. In this paper, an error correction method reflecting the error characteristic is presented. This method detects errors by a binary ECC as a conventional manner, but a nonbinary value or whole the bits in a cell, are subjected to error correction, so as to be corrected into the most probable neighborhood value. The amount of bit error rate (BER) improvement is depending on the probability of the each error magnitude. In case of 2bit/cell, if only errors of magnitude 1 and 2 can occur and the latter occupies 5% of cell errors, acceptable BER is improved by 4%. This is corresponding to extending 2.4% of endurance. This method needs about 15% longer average latency, 19% longer maximum latency, and 15% lower throughput. However, with using the conventional method until the memories' lifetime number of program/erase cycling, and the proposed method after that, BER improvement can be utilized for extending endurance without latency and throughput degradation until the switch of the methods.