A novel design technique for two-dimensional (2-D) waveguide slot arrays is proposed in this paper that combines a full-wave method of moments (MoM) analysis and an equivalent circuit with the explicit restraint of input matching. The admittance and slot spacing are determined first in an equivalent circuit to realize the desired distribution of power dissipation and phase, with the explicit restraint of input matching. Secondly by applying a full-wave MoM analysis to the finite 2-D array, slot parameters are iteratively determined to realize the active admittance designed above where slot mutual coupling and wall thickness are fully taken into account. The admittance, treated as the key parameter in the equivalent circuit corresponds to the power dissipation of the slots but not to the slot voltage, which is directly synthesized from the radiation pattern. The initial value of the power dissipation is assumed to be proportional to the square of the amplitude of the desired slot voltage. This assumption leads to a feedback procedure, because the resultant slot voltage distribution generally differs from the desired ones due to the effect of non-uniformity in the characteristic impedance on slot apertures. This slot voltage error is used to renew the initial distribution of power dissipation in the equivalent circuit. Generally, only one feedback cycle is needed. Two 2427-element arrays with uniform and Taylor distributions were designed and fabricated at 25.3 GHz. The measured overall reflections for both antennas were suppressed below -18 dB over the 24.3-26.3 GHz frequency range. High aperture efficiencies of 86.8% and 55.1% were realized for the antennas with uniform and Taylor distributions, the latter of which has very low sidelobes below -33 dB in both the E- and H-planes.

In the design of cascode CMOS low-noise amplifiers, the gate-drain capacitance is generally neglected because it is thought to be small enough compared to gate-source capacitance. However, a careful examination will reveal the fact that the drain impedance of the input transistor significantly affects the input impedance through the gate-drain capacitance, especially as the CMOS technology getting more and more advanced. Moreover, the substrate coupling network of the input transistor also comes into play when the drain impedance of the input transistor is high enough compared to the substrate coupling network. In order to make input matching easier, it is desirable to know the details of the substrate coupling network. Unfortunately, designers generally do not have enough information about the technology they have used, not to mention knowing the details concerning the substrate coupling network. As a matter of fact, designers generally do have foundry provided component models that contain information about the substrate coupling network. This gives us the chance to minimize its effect and predict the input impedance of a low noise amplifier more accurately. In this paper, we show that the effect of the substrate coupling network can be ignored by keeping the drain impedance of the input transistor low enough and a proper drain impedance can then be chosen to achieve input matching without the need of iteration steps. Simulation results of a 2.4 GHz CMOS low noise amplifier using foundry provided component models are also presented to demonstrate the validation of the proposed input matching method.