We propose a novel mobility reduction cancellation technique for an OTA (Operational Transconductance Amplifier). The proposed technique can be easily realized by using conventional OTAs. The proposed OTAs have good linearity. The simulation results show that the THD is less than 1% for 1.8 Vp-p at 3 V supply voltage.

This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.