In this letter, a design method of linear-phase paraunitary filter banks is proposed for an odd number of channels. In the proposed method, a non-linear unconstrained optimization process is assumed to be applied to a lattice structure which makes the starting guess of design parameters simple. In order to avoid insignificant local minimum solutions, a recursive initialization procedure is proposed. The significance of our proposed method is verified by some design examples.

In this paper, a post-layout optimization technique for power dissipation and timing of cell-based Bipolar ECL LSIs is proposed. An ECL LSI can operate at a frequency of a few GHz but the power dissipation is very high compared to CMOS LSIs, which makes the systems using ECL quite expensive. Therefore it is crucial to develop of CAD techniques that minimize the power dissipation of an ECL LSI without decreasing its performance. To begin with, power and delay models of an ECL gate are presented as functions of its switching current. The power dissipation is a linear function of the switching current and the delay time is its hyperbolic function. These functions are obtained considering the post-layout interconnect capacitance and resistance to make the optimization results accurate enough. Using the delay model, a set of timing constraints specifying the max/min cell delay and the clock skew are extracted. This set of constraints in then given to a nonlinear programming package. The objective functions are clock skew time, the clock cycle time and the power dissipation, which are optimized in this order. With the minimum delay and hold constraints, the problem is not convex so that conventional convex programming approach cannot be used. As a result of the optimization, the switching currents for cells are obtained. These are realized within cells by regulating programmable resistors", which is a special feature of our ECL cell library. Since the above optimization is carried out after the placement and routing of the circuit, it can take accurate delay and power estimation into consideration. Experimental results show more than 40% power reductions for circuits including a real communication system chip, compared to the max power versions. The clock cycle time was maintained or even made faster due to the efficient clock skew optimization.

A least squares approximation method of recursive digital filters for finite interval response with zero value outside the interval is presented. According to the characteristic of the method, the modified Gauss Method is utilized in iteratively determining design parameters. Convergence, together with the stability of the resulting filter, are guaranteed.