The polycrystalline silicon (poly-Si) TFT has two insulator interfaces between the polycrystalline silicon and front and back insulators. These interfaces have trap states, which affect the characteristics of poly-Si TFT. In the silicon-on-insulator (SOI) technology area, using the dual-gated, fully-depleted SOI MOSFET under the depleted back-channel condition, the back-interface trap density can be calculated through the front-channel threshold voltage and film thicknesses. The front-interface trap density is also evaluated changing the roles of both gates. This evaluation method for front- and back- interface trap densities is called the threshold-voltage method. To apply this threshold-voltage method to the "medium-thickness" poly-Si TFT, of which the channel is not fully depleted in normal single gate bias operation, the biases for both front and back gates are controlled to realize full depletion. Under the fully-depleted condition, the front- or back- threshold voltage of poly-Si TFT is carefully extracted by the second-derivative method changing back- and front- gate biases. We evaluated the front- and back- interface trap densities not only for normal operation but also under stress. To evaluate the bias and temperature stress effect, we used two types of samples, which are made by different processes. The evaluated front- and back- interface trap densities for both samples in initial state are around 51011 to 1.31012 cm-2eV-1, which are almost the same as the reported values. Applying bias and temperature stress shows the variation of these interface-trap densities. Samples with large shifts of the front-channel threshold voltage show large trap density variation. On the other hand, samples with small threshold voltage shifts show small trap density variation. The variation of the back-interface trap density during the stress application showed a correlation to the front-channel threshold voltage shift.

We have proposed and fabricated a new poly-Si TFT employing the selectively doped regions in the active layer. In the proposed poly-Si TFTs, the selectively doped regions where doping concentration is identical to that of the source/drain, reduce the effective channel length during the on-state. Under the off-state, the selectively doped regions may reduce the lateral electric field induced near the drain and reduce the leakage current considerably. The experimental data of the proposed TFT exhibit high on-current, low leakage current and low threshold voltage. The fabrication of the proposed TFT is rather simple; the required steps for the proposed TFT are reduced because high dosage ion-implantation for the source/drain and the selectively doped regions is performed simultaneously prior to excimer laser irradiation step.