Recently, H-bridge pulse width modulation (PWM) micro-stepping motor drivers have been widely used for 3-D printers, robots, and medical instruments. Differently from a simple PWM motor driver circuit, the H-bridge PWM micro-stepping motor driver circuit can generate radio frequency (RF) electromagnetic interference (EMI) noises of up to several hundred MHz frequencies, due to digital interface circuits and a high-performance CPU. For medical instrument systems, the minimization of EMI noises can assure operating safety and greatly reduce the chance of malfunction between instruments. This work proposes a passive-filter configuration-based circuit design for reducing up-to-several-hundred-MHz EMI noises generated from the H-bridge PWM micro-stepping motor driver circuit. More specifically, the proposed RF EMI reduction approach consists of proper passive filter design, shielding in motor wires, and common ground design in the print circuit board. The proposed passive filter configuration design is validated through the overall reduction of EMI noises at RF band. Finally, the proposed EMI reduction approach is tested experientially through a prototype and about 16 dB average reduction of RF EMI noises is demonstrated.

This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-µm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5-0.2µm scaled CMOS devices.