A diagnosis testbench of analog IP cores characterizes their coupling strengths against on-chip environmental disturbances, specifically with regard to substrate voltage variations. The testbench incorporates multi-tone digital noise generators and a precision waveform capture with multiple probing channels. A prototype test bench fabricated in a 90-nm CMOS technology demonstrates the diagnosis of substrate coupling up to 400 MHz with dynamic range of more than 60 dB. The coefficients of noise propagation as well as noise coupling on a silicon substrate are quantitatively derived for analog IP cores processed in a target technology, and further linked with noise awared EDA tooling for the successful adoption of such IP cores in SoC integration.

This paper presents a low-power small-area-overhead physical random number generator utilizing SAR ADC embedded in sensor SoCs. An unpredictable random bit sequence is produced by an existing comparator in typical SAR ADCs, which results in little area overhead. Unlike the other comparator-based physical random number generator, this proposed technique does not require an offset calibration scheme since SAR binary search algorithm automatically converges the two input voltages of the comparator to balance the differential circuit pair. Although the randomness slightly depends on an quantization error due to sharing AD conversion scheme, the input signal distribution enhances the quality of random number bit sequence which can use for various security countermeasures such as masking techniques. Fabricated in 180nm CMOS, 1Mb/s random bit generator achieves high efficiency of 0.72pJ/bit with only 400μm2 area overhead, which occupies less than 0.5% of SAR ADC, while remaining 10-bit AD conversion function.

Power supply noise waveforms are acquired in a voltage domain by an on-chip monitor at resolutions of 0.3 ns/1.2 mV, in a digital test circuit consisting of 0.18-µm CMOS standard logic cells. Concurrently, magnetic field variation on a printed circuit board (PCB) due to power supply current of the test circuit is measured by an off-chip magnetic probing technique. An equivalent circuit model that unifies on- and off-chip impedance network of the entire test setup for EMI analysis is used for calculating the on-chip voltage-mode power supply noise from the off-chip magnetic field measurements. We have confirmed excellent consistency in frequency components of power supply noises up to 300 MHz among those derived by the on-chip direct sensing and the off-chip magnetic probing techniques. These results not only validate the state-of-the art EMI analysis methodology but also promise its connectivity with on-chip power supply integrity analysis at the integrated circuit level, for the first time in both technical fields.

Substrate noise coupling has been seriously concerned in the design of advanced analog and radio frequency (RF) integrated circuits (ICs). This paper reviews recent advancements in the modeling, analysis, and evaluation of substrate noise coupling at IC chip level. Noise generation from digital circuits and propagation to the area of analog circuits are clearly visualized both by full-chip simulation as well as by on-chip measurements, for silicon test vehicles. The impacts of substrate noise coupling are also in-depth discussed at device, circuit, as well as system levels. Overall understanding of substrate noise coupling will then provide the basics for highly reliable design of analog and RF ICs.

This paper proposes a nonlinear oscillator network model for gray-level image segmentation suitable for massively parallel VLSI implementation. The model performs image segmentation in parallel using nonlinear analog dynamics. Because of the limited calculation precision in VLSI implementation, it is important to estimate the calculation precision required for proper operation. By numerical simulation, the necessary precision is estimated to be 5 bits. We propose a nonlinear oscillator network circuit using the pulse modulation approach suitable for an analog-digital merged circuit architecture. The basic operations of the nonlinear oscillator circuit and the connection weight circuit are confirmed by SPICE circuit simulation. The circuit simulation results also demonstrate that image segmentation can be performed within the order of 100 µs.

We have developed a 32-bit, 32-word, and 9-read, 7-write ported register file. This register file has several circuits and techniques for reducing the impact of process variation that is marked in recent process technologies, voltage variation, and temperature variation, so called PVT variation. We describe these circuits and techniques in detail, and confirm their effects by simulation and measurement of the test chip.

This paper proposes non-volatile analog memory circuits using pulse-width modulation (PWM) methods. The conventional analog memory using floating gate device has a trade-off between programming speed and precision because of the constant width of write pulses. The proposed circuits attain high programming speed with high precision by using PWM write pulses. Three circuits are proposed and their performance is evaluated using SPICE simulation. The simulation results show that fast programming time less than 20 µs, high updating resolution of 11 bits, and high precision more than 7 bits are achieved.

This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-µm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5-0.2µm scaled CMOS devices.

Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.

This paper presents circuit techniques using pulse-width and pulse-phase modulation (PWM/PPM) approaches for VLSI implementation of nonlinear dynamical systems. The proposed circuits implement discrete-time continuous-state dynamics by means of analog processing in a time domain, and also approximately implement continuous-time dynamics. Arbitrary nonlinear transformation functions are generated by the process in which a PPM signal samples a voltage or current source whose waveform in the time domain has the same shape as the desired transformation function. Because a shared arbitrary nonlinear voltage or current waveform generator can be constructed by digital circuits and D/A converters, high flexibility and real-time controllability are achieved. By using one of these new techniques, we have designed and fabricated a CMOS chaos circuit with arbitrary 1-D maps using a 0.6 µm CMOS process, and demonstrate from the experimental results that the new chaos circuit successfully generated various chaos with 7.5-7.8 bit precision by using logistic, tent and chaotic-neuron maps.

Impacts of electromagnetic (EM) interference (immunity) on operation of LSI circuits in a QFP-packaged and PCB-mounted environment are studied. EM power injection to a power-supply system leads to malfunction, where the power is translated into voltage bounces through combined on- and off- chip impedances, affecting power supply and ground, as well as signal nodes in a die, seen from on-chip waveform measurements. A lumped power-supply impedance model and the minimum amplitude of voltage bounce induced by EM power for malfunction, both of which can be derived from external measurements to a given packaged LSI, formulate an EM interference model that is helpful in the PCB design toward high immunity. The technique can be generally applied to systems-on-chip applications.

In-place AC measurements of the signal gain and substrate sensitivity of differential pair transistors of an analog amplifier are combined with DC characterization of the threshold voltage (Vth) of the same transistors. An on-chip continuous time waveform monitoring technique enables in-place matrix measurements of differential pair transistors with a variety of channel sizes and geometry, allowing the wide coverage of experiments about the transistor-level physical layout dependency of substrate noise response. A prototype test structure uses a 90-nm CMOS technology and demonstrates the geometry-dependent variation of substrate sensitivity of transistors in operation.

This paper presents a neural circuit using PWM technique based on an analog-digital merged circuit architecture. Some new PWM circuit techniques are proposed. A bipolar-weighted summation circuit is described which attains 8-bit precision in SPICE simulation at 5 V supply voltage by compensating parasitic capacitance effects. A high performance differential-type latch comparator which can discriminate 1 mV difference at 100 MHz in SPICE simulation is also described. Next, we present a prototype chip fabricated using a 0.6µm CMOS process. The measurement results demonstrate that the overall precision in the weighted summation and the sigmoidal transformation is 5 bits. A neural network has been constructed using the prototype chips, and the experimental results for realizing the XOR function have successfully verified the basic neural operation.

A continuous-time waveform monitoring technique for quality on-chip power noise measurements features matched probing performance among a variety of voltage domains of interest in a VLSI circuit, covering digital Vdd, analog Vdd, as well as at Vss, and multiple probing capability at various locations on power planes. A calibration flow eliminates the offset as well as gain errors among probing channels. The consistency of waveforms acquired by the proposed continuous-time monitoring and sampled-time precise digitization techniques is ensured. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with 200 mV at 2.5 V, 1.0 V, and 0.0 V, respectively, with less than 4 mV deviation among 240 probing channels.

With increasing technology scaling and the use of lower voltages, more research interest is being shown in variability-tolerant analog front end design. In this paper, we describe an adaptive amplitude control transmitter that is operated using differential signaling to reduce the temperature variability effect. It enables low power, low voltage operation by synergy between adaptive amplitude control and Vth temperature variation control. It is suitable for high-speed interface applications, particularly cable interfaces. By installing an aggressor circuit to estimate transmitter jitter and changing its frequency and activation rate, we were able to analyze the effects of the interface block on the input buffer and thence on the entire system. We also report a detailed estimation of the receiver clock-data recovery (CDR) operation for transmitter jitter estimation. These investigations provide suggestions for widening the eye opening of the transmitter.

This paper proposes a new associative memory architecture using stochastic behavior in single electron tunneling (SET) devices. This memory stochastically extracts the pattern most similar to the input key pattern from the stored patterns in two matching modes: the voltage-domain matching mode and the time-domain one. In the former matching mode, ordinary associative memory operation can be performed. In the latter matching mode, a purely stochastic search can be performed. Even in this case, by repeating numerous searching trials, the order of similarity can be obtained. We propose a circuit using SET devices based on this architecture and demonstrate its basic operation with a simulation. By feeding the output pattern back to the input, this memory retrieves slightly dissimilar patterns consecutively. This function may be the key to developing highly intelligent information processing systems close to the human brain.

This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of Vdd and it provides 91 times better failure rate with a 35% droop of Vdd compared with the conventional design.

An LSI Chip-Package-Board integrated power noise simulation model and its validity is discussed in this paper. A unified power delivery network (PDN) of LSI chip, package, and printed circuit board (PCB) is connected with on-chip power supply current models with capacitor charging expression. The proposed modeling flow is demonstrated for the 32-bit microprocessor in a 1.0V 90nm CMOS technology. The PDN of the system that includes a chip, bonding wires and a printed circuit board is modeled in an equivalent circuit. The on-chip power supply noise monitoring technique and the magnetic probe method is applied for validating simulation results. Simulations and measurements explore power supply noise generation with the dependency on operating frequencies in the wide range from 10MHz to 300MHz, under the operation mode of dynamic frequency scaling, and in the long time operation with various operation codes. It is confirmed that the proposed power supply noise simulation model is helpful for the noise estimation throughout the design phase of the LSI system.