A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits

Yoji BANDO; Satoshi TAKAYA; Toru OHKAWA; Toshiharu TAKARAMOTO; Toshio YAMADA; Masaaki SOUDA; Shigetaka KUMASHIRO; Tohru MOGAMI; Makoto NAGATA

doi:10.1587/transele.E94.C.495

A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits

Yoji BANDO, Satoshi TAKAYA, Toru OHKAWA, Toshiharu TAKARAMOTO, Toshio YAMADA, Masaaki SOUDA, Shigetaka KUMASHIRO, Tohru MOGAMI, Makoto NAGATA

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A continuous-time waveform monitoring technique for quality on-chip power noise measurements features matched probing performance among a variety of voltage domains of interest in a VLSI circuit, covering digital Vdd, analog Vdd, as well as at Vss, and multiple probing capability at various locations on power planes. A calibration flow eliminates the offset as well as gain errors among probing channels. The consistency of waveforms acquired by the proposed continuous-time monitoring and sampled-time precise digitization techniques is ensured. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with 200 mV at 2.5 V, 1.0 V, and 0.0 V, respectively, with less than 4 mV deviation among 240 probing channels.

Publication: IEICE TRANSACTIONS on Electronics Vol.E94-C No.4 pp.495-503

Publication Date: 2011/04/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E94.C.495

Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)

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Yoji BANDO, Satoshi TAKAYA, Toru OHKAWA, Toshiharu TAKARAMOTO, Toshio YAMADA, Masaaki SOUDA, Shigetaka KUMASHIRO, Tohru MOGAMI, Makoto NAGATA, "A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits" in IEICE TRANSACTIONS on Electronics, vol. E94-C, no. 4, pp. 495-503, April 2011, doi: 10.1587/transele.E94.C.495.
Abstract: A continuous-time waveform monitoring technique for quality on-chip power noise measurements features matched probing performance among a variety of voltage domains of interest in a VLSI circuit, covering digital Vdd, analog Vdd, as well as at Vss, and multiple probing capability at various locations on power planes. A calibration flow eliminates the offset as well as gain errors among probing channels. The consistency of waveforms acquired by the proposed continuous-time monitoring and sampled-time precise digitization techniques is ensured. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with 200 mV at 2.5 V, 1.0 V, and 0.0 V, respectively, with less than 4 mV deviation among 240 probing channels.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.495/_p

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@ARTICLE{e94-c_4_495,
author={Yoji BANDO, Satoshi TAKAYA, Toru OHKAWA, Toshiharu TAKARAMOTO, Toshio YAMADA, Masaaki SOUDA, Shigetaka KUMASHIRO, Tohru MOGAMI, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits},
year={2011},
volume={E94-C},
number={4},
pages={495-503},
abstract={A continuous-time waveform monitoring technique for quality on-chip power noise measurements features matched probing performance among a variety of voltage domains of interest in a VLSI circuit, covering digital Vdd, analog Vdd, as well as at Vss, and multiple probing capability at various locations on power planes. A calibration flow eliminates the offset as well as gain errors among probing channels. The consistency of waveforms acquired by the proposed continuous-time monitoring and sampled-time precise digitization techniques is ensured. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with 200 mV at 2.5 V, 1.0 V, and 0.0 V, respectively, with less than 4 mV deviation among 240 probing channels.},
keywords={},
doi={10.1587/transele.E94.C.495},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 495
EP - 503
AU - Yoji BANDO
AU - Satoshi TAKAYA
AU - Toru OHKAWA
AU - Toshiharu TAKARAMOTO
AU - Toshio YAMADA
AU - Masaaki SOUDA
AU - Shigetaka KUMASHIRO
AU - Tohru MOGAMI
AU - Makoto NAGATA
PY - 2011
DO - 10.1587/transele.E94.C.495
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - A continuous-time waveform monitoring technique for quality on-chip power noise measurements features matched probing performance among a variety of voltage domains of interest in a VLSI circuit, covering digital Vdd, analog Vdd, as well as at Vss, and multiple probing capability at various locations on power planes. A calibration flow eliminates the offset as well as gain errors among probing channels. The consistency of waveforms acquired by the proposed continuous-time monitoring and sampled-time precise digitization techniques is ensured. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with 200 mV at 2.5 V, 1.0 V, and 0.0 V, respectively, with less than 4 mV deviation among 240 probing channels.
ER -